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+ Missing part of internal ARM assembler, Mantis #26588. I'm not setting it as default for arm-wince yet, because testing reveals several points in generic code that need adjustments.

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git-svn-id: trunk@29588 -
This commit is contained in:
sergei 2015-01-30 22:45:05 +00:00
parent 2c3aa7cee0
commit 9cc0bdd6b9
5 changed files with 458 additions and 238 deletions
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293
compiler/arm/aasmcpu.pas
View File

@ -1595,6 +1595,12 @@ implementation
if (ot and OT_AM2)<>0 then if (ot and OT_AM2)<>0 then
s:=s+' am2 '; s:=s+' am2 ';
end end
else
if (ot and OT_SHIFTEROP)=OT_SHIFTEROP then
begin
s:=s+'shifterop';
addsize:=false;
end
else else
s:=s+'???'; s:=s+'???';
{ size } { size }
@ -1867,6 +1873,8 @@ implementation
begin begin
ot:=OT_SHIFTEROP; ot:=OT_SHIFTEROP;
end; end;
top_conditioncode:
ot:=OT_CONDITION;
else else
internalerror(2004022623); internalerror(2004022623);
end; end;
@ -1900,7 +1908,6 @@ implementation
{siz : array[0..3] of longint;} {siz : array[0..3] of longint;}
begin begin
Matches:=100; Matches:=100;
writeln(getstring,'---');
{ Check the opcode and operands } { Check the opcode and operands }
if (p^.opcode<>opcode) or (p^.ops<>ops) then if (p^.opcode<>opcode) or (p^.ops<>ops) then
@ -1942,7 +1949,7 @@ implementation
{ update condition flags { update condition flags
or floating point single } or floating point single }
if (oppostfix=PF_S) and if (oppostfix=PF_S) and
not(p^.code[0] in [#$04]) then not(p^.code[0] in [#$04..#$0B]) then
begin begin
Matches:=0; Matches:=0;
exit; exit;
@ -2113,26 +2120,58 @@ implementation
procedure taicpu.gencode(objdata:TObjData); procedure taicpu.gencode(objdata:TObjData);
const
CondVal : array[TAsmCond] of byte=(
$E, $0, $1, $2, $3, $4, $5, $6, $7, $8, $9, $A,
$B, $C, $D, $E, 0);
var var
bytes : dword; bytes : dword;
i_field : byte; i_field : byte;
currsym : TObjSymbol;
offset : longint;
procedure setshifterop(op : byte); procedure setshifterop(op : byte);
var
r : byte;
imm : dword;
begin begin
case oper[op]^.typ of case oper[op]^.typ of
top_const: top_const:
begin begin
i_field:=1; i_field:=1;
bytes:=bytes or dword(oper[op]^.val and $fff); if oper[op]^.val and $ff=oper[op]^.val then
bytes:=bytes or dword(oper[op]^.val)
else
begin
{ calc rotate and adjust imm }
r:=0;
imm:=dword(oper[op]^.val);
repeat
imm:=RolDWord(imm, 2);
inc(r)
until imm and $ff=imm;
bytes:=bytes or (r shl 8) or imm;
end;
end; end;
top_reg: top_reg:
begin begin
i_field:=0; i_field:=0;
bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16); bytes:=bytes or getsupreg(oper[op]^.reg);
{ does a real shifter op follow? } { does a real shifter op follow? }
if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then if (op+1<opercnt) and (oper[op+1]^.typ=top_shifterop) then
with oper[op+1]^.shifterop^ do
begin begin
bytes:=bytes or (shiftimm shl 7);
if shiftmode<>SM_RRX then
bytes:=bytes or (ord(shiftmode) - ord(SM_LSL)) shl 5
else
bytes:=bytes or (3 shl 5);
if getregtype(rs) <> R_INVALIDREGISTER then
begin
bytes:=bytes or (1 shl 4);
bytes:=bytes or (getsupreg(rs) shl 8);
end
end; end;
end; end;
else else
@ -2140,34 +2179,258 @@ implementation
end; end;
end; end;
function MakeRegList(reglist: tcpuregisterset): word;
var
i, w: word;
begin
result:=0;
w:=1;
for i:=RS_R0 to RS_R15 do
begin
if i in reglist then
result:=result or w;
w:=w shl 1
end;
end;
begin begin
bytes:=$0; bytes:=$0;
i_field:=0; i_field:=0;
{ evaluate and set condition code } { evaluate and set condition code }
bytes:=bytes or (CondVal[condition] shl 28);
{ condition code allowed? } { condition code allowed? }
{ setup rest of the instruction } { setup rest of the instruction }
case insentry^.code[0] of case insentry^.code[0] of
#$08: #$01: // B/BL
begin begin
{ set instruction code } { set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 26); bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 21); { set offset }
currsym:=objdata.symbolref(oper[0]^.ref^.symbol);
if (currsym.bind<>AB_LOCAL) and (currsym.objsection<>objdata.CurrObjSec) then
objdata.writereloc(oper[0]^.ref^.offset,0,currsym,RELOC_RELATIVE_24)
else
bytes:=bytes or (((currsym.offset-insoffset-8) shr 2) and $ffffff);
end;
#$04..#$07: // SUB
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
{ set destination } { set destination }
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12); bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
{ set Rn }
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 16);
{ create shifter op } { create shifter op }
setshifterop(1); setshifterop(2);
{ set I field }
{ set i field }
bytes:=bytes or (i_field shl 25); bytes:=bytes or (i_field shl 25);
{ set S if necessary }
{ set s if necessary }
if oppostfix=PF_S then if oppostfix=PF_S then
bytes:=bytes or (1 shl 20); bytes:=bytes or (1 shl 20);
end; end;
#$08,#$0A,#$0B: // MOV
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
{ set destination }
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
{ create shifter op }
setshifterop(1);
{ set I field }
bytes:=bytes or (i_field shl 25);
{ set S if necessary }
if oppostfix=PF_S then
bytes:=bytes or (1 shl 20);
end;
#$0C,#$0E,#$0F: // CMP
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
{ set destination }
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
{ create shifter op }
setshifterop(1);
{ set I field }
bytes:=bytes or (i_field shl 25);
{ always set S bit }
bytes:=bytes or (1 shl 20);
end;
#$14: // MUL/MLA r1,r2,r3
begin
{ set instruction code }
bytes:=bytes or ord(insentry^.code[1]) shl 24;
bytes:=bytes or ord(insentry^.code[2]) shl 16;
bytes:=bytes or ord(insentry^.code[3]);
{ set regs }
bytes:=bytes or getsupreg(oper[0]^.reg) shl 16;
bytes:=bytes or getsupreg(oper[1]^.reg);
bytes:=bytes or getsupreg(oper[2]^.reg) shl 8;
end;
#$15: // MUL/MLA r1,r2,r3,r4
begin
{ set instruction code }
bytes:=bytes or ord(insentry^.code[1]) shl 24;
bytes:=bytes or ord(insentry^.code[2]) shl 16;
bytes:=bytes or ord(insentry^.code[3]);
{ set regs }
bytes:=bytes or getsupreg(oper[0]^.reg) shl 16;
bytes:=bytes or getsupreg(oper[1]^.reg);
bytes:=bytes or getsupreg(oper[2]^.reg) shl 8;
bytes:=bytes or getsupreg(oper[3]^.reg) shl 12;
end;
#$16: // MULL r1,r2,r3,r4
begin
{ set instruction code }
bytes:=bytes or ord(insentry^.code[1]) shl 24;
bytes:=bytes or ord(insentry^.code[2]) shl 16;
bytes:=bytes or ord(insentry^.code[3]);
{ set regs }
bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
bytes:=bytes or getsupreg(oper[1]^.reg) shl 16;
bytes:=bytes or getsupreg(oper[2]^.reg);
bytes:=bytes or getsupreg(oper[3]^.reg) shl 8;
end;
#$17: // LDR/STR
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
{ set Rn and Rd }
bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
begin
{ set offset }
offset:=0;
currsym:=objdata.symbolref(oper[1]^.ref^.symbol);
if assigned(currsym) then
offset:=currsym.offset-insoffset-8;
offset:=offset+oper[1]^.ref^.offset;
if offset>=0 then
begin
{ set U flag }
bytes:=bytes or (1 shl 23);
bytes:=bytes or offset
end
else
begin
offset:=-offset;
bytes:=bytes or offset
end;
end
else
begin
{ set U flag }
if oper[1]^.ref^.signindex>0 then
bytes:=bytes or (1 shl 23);
{ set I flag }
bytes:=bytes or (1 shl 25);
bytes:=bytes or getsupreg(oper[1]^.ref^.index);
{ set shift }
with oper[1]^.ref^ do
if shiftmode<>SM_None then
begin
bytes:=bytes or (shiftimm shl 7);
if shiftmode<>SM_RRX then
bytes:=bytes or (ord(shiftmode) - ord(SM_LSL)) shl 5
else
bytes:=bytes or (3 shl 5);
end
end;
{ set W bit }
if oper[1]^.ref^.addressmode=AM_PREINDEXED then
bytes:=bytes or (1 shl 21);
{ set P bit if necessary }
if oper[1]^.ref^.addressmode<>AM_POSTINDEXED then
bytes:=bytes or (1 shl 24);
end;
#$22: // LDRH/STRH
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 16);
bytes:=bytes or ord(insentry^.code[2]);
{ src/dest register (Rd) }
bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
{ base register (Rn) }
bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
begin
bytes:=bytes or (1 shl 22); // with immediate offset
if oper[1]^.ref^.offset < 0 then
begin
bytes:=bytes or ((-oper[1]^.ref^.offset) and $f0 shl 4);
bytes:=bytes or ((-oper[1]^.ref^.offset) and $f);
end
else
begin
{ set U bit }
bytes:=bytes or (1 shl 23);
bytes:=bytes or (oper[1]^.ref^.offset and $f0 shl 4);
bytes:=bytes or (oper[1]^.ref^.offset and $f);
end;
end
else
begin
{ set U flag }
bytes:=bytes or (1 shl 23);
bytes:=bytes or getsupreg(oper[1]^.ref^.index);
end;
{ set W bit }
if oper[1]^.ref^.addressmode=AM_PREINDEXED then
bytes:=bytes or (1 shl 21);
{ set P bit if necessary }
if oper[1]^.ref^.addressmode<>AM_POSTINDEXED then
bytes:=bytes or (1 shl 24);
end;
#$26: // LDM/STM
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 20);
if oper[0]^.typ=top_ref then
begin
{ set W bit }
if oper[0]^.ref^.addressmode=AM_PREINDEXED then
bytes:=bytes or (1 shl 21);
{ set Rn }
bytes:=bytes or (getsupreg(oper[0]^.ref^.index) shl 16);
end
else { typ=top_reg }
begin
{ set Rn }
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
end;
{ reglist }
bytes:=bytes or MakeRegList(oper[1]^.regset^);
{ set P bit }
if (opcode=A_LDM) and (oppostfix in [PF_ED,PF_EA,PF_IB,PF_DB])
or (opcode=A_STM) and (oppostfix in [PF_FA,PF_FD,PF_IB,PF_DB]) then
bytes:=bytes or (1 shl 24);
{ set U bit }
if (opcode=A_LDM) and (oppostfix in [PF_ED,PF_FD,PF_IB,PF_IA])
or (opcode=A_STM) and (oppostfix in [PF_FA,PF_EA,PF_IB,PF_IA]) then
bytes:=bytes or (1 shl 23);
end;
#$27: // SWP/SWPB
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 20);
bytes:=bytes or (ord(insentry^.code[2]) shl 4);
{ set regs }
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
bytes:=bytes or getsupreg(oper[1]^.reg);
bytes:=bytes or (getsupreg(oper[2]^.ref^.base) shl 16);
end;
#$03: // BX
begin
writeln(objdata.CurrObjSec.fullname);
Comment(v_warning,'BX instruction');
// TBD
end;
#$ff: #$ff:
internalerror(2005091101); internalerror(2005091101);
else else

110
compiler/arm/armins.dat
View File

@ -97,13 +97,13 @@ void void none
reg32,reg32,reg32 \4\x0\xA0 ARM7 reg32,reg32,reg32 \4\x0\xA0 ARM7
reg32,reg32,reg32,reg32 \5\x0\xA0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xA0 ARM7
reg32,reg32,reg32,imm \6\x0\xA0 ARM7 reg32,reg32,reg32,imm \6\x0\xA0 ARM7
reg32,reg32,imm \7\x2\xA0 ARM7 reg32,reg32,immshifter \7\x2\xA0 ARM7
[ADDcc] [ADDcc]
reg32,reg32,reg32 \4\x0\x80 ARM7 reg32,reg32,reg32 \4\x0\x80 ARM7
reg32,reg32,reg32,reg32 \5\x0\x80 ARM7 reg32,reg32,reg32,reg32 \5\x0\x80 ARM7
reg32,reg32,reg32,imm \6\x0\x80 ARM7 reg32,reg32,reg32,shifterop \6\x0\x80 ARM7
reg32,reg32,imm \7\x2\x80 ARM7 reg32,reg32,immshifter \7\x2\x80 ARM7
[ADFcc] [ADFcc]
@ -111,19 +111,20 @@ reg32,reg32,imm \7\x2\x80 ARM7
[ANDcc] [ANDcc]
reg32,reg32,reg32 \4\x0\x00 ARM7 reg32,reg32,reg32 \4\x0\x00 ARM7
reg32,reg32,reg32,reg32 \5\x0\x00 ARM7 ;reg32,reg32,reg32,reg32 \5\x0\x00 ARM7
reg32,reg32,reg32,imm \6\x0\x00 ARM7 ;reg32,reg32,reg32,imm \6\x0\x00 ARM7
reg32,reg32,imm \7\x2\x00 ARM7 reg32,reg32,reg32,shifterop \6\x0\x00 ARM7
reg32,reg32,immshifter \7\x2\x00 ARM7
[Bcc] [Bcc]
mem32 \1\x0A ARM7 mem32 \1\x0A ARM7
imm24 \1\x0A ARM7 imm24 \1\x0A ARM7
[BICcc] [BICcc]
reg32,reg32,reg32 \4\x1\xC0 ARM7 ;reg32,reg32,reg32 \4\x1\xC0 ARM7
reg32,reg32,reg32,reg32 \5\x1\xC0 ARM7 ;reg32,reg32,reg32,reg32 \5\x1\xC0 ARM7
reg32,reg32,reg32,imm \6\x1\xC0 ARM7 ;reg32,reg32,reg32,imm \6\x1\xC0 ARM7
reg32,reg32,imm \7\x3\xC0 ARM7 reg32,reg32,immshifter \7\x3\xC0 ARM7
[BLcc] [BLcc]
mem32 \1\x0B ARM7 mem32 \1\x0B ARM7
@ -149,13 +150,13 @@ reg8,reg8 \300\1\x10\101 ARM7
reg32,reg32 \xC\x1\x60 ARM7 reg32,reg32 \xC\x1\x60 ARM7
reg32,reg32,reg32 \xD\x1\x60 ARM7 reg32,reg32,reg32 \xD\x1\x60 ARM7
reg32,reg32,imm \xE\x1\x60 ARM7 reg32,reg32,imm \xE\x1\x60 ARM7
reg32,imm \xF\x3\x60 ARM7 reg32,immshifter \xF\x1\x60 ARM7
[CMPcc] [CMPcc]
reg32,reg32 \xC\x1\x40 ARM7 reg32,reg32 \xC\x1\x40 ARM7
reg32,reg32,reg32 \xD\x1\x40 ARM7 reg32,reg32,reg32 \xD\x1\x40 ARM7
reg32,reg32,imm \xE\x1\x40 ARM7 reg32,reg32,shifterop \xE\x1\x40 ARM7
reg32,imm \xF\x3\x40 ARM7 reg32,immshifter \xF\x3\x40 ARM7
[CLZcc] [CLZcc]
reg32,reg32 \x27\x01\x01 ARM7 reg32,reg32 \x27\x01\x01 ARM7
@ -172,9 +173,10 @@ reg32,reg32 \x27\x01\x01 ARM7
[EORcc] [EORcc]
reg32,reg32,reg32 \4\x0\x20 ARM7 reg32,reg32,reg32 \4\x0\x20 ARM7
reg32,reg32,reg32,reg32 \5\x0\x20 ARM7 ;reg32,reg32,reg32,reg32 \5\x0\x20 ARM7
reg32,reg32,reg32,imm \6\x0\x20 ARM7 ;reg32,reg32,reg32,imm \6\x0\x20 ARM7
reg32,reg32,imm \7\x2\x20 ARM7 reg32,reg32,reg32,shifterop \6\x0\x20 ARM7
reg32,reg32,immshifter \7\x2\x20 ARM7
[EXPcc] [EXPcc]
@ -193,14 +195,15 @@ reg32,reg32 \321\300\1\x11\101 ARM7
[LDMcc] [LDMcc]
memam4,reglist \x26\x81 ARM7 memam4,reglist \x26\x81 ARM7
reg32,reglist \x26\x81 ARM7
[LDRBTcc] [LDRBTcc]
[LDRBcc] [LDRBcc]
reg32,memam2 \x17\x07\x10 ARM7 reg32,memam2 \x17\x04\x50 ARM7
[LDRcc] [LDRcc]
reg32,memam2 \x17\x05\x10 ARM7 reg32,memam2 \x17\x04\x10 ARM7
; reg32,imm32 \x17\x05\x10 ARM7 ; reg32,imm32 \x17\x05\x10 ARM7
; reg32,reg32 \x18\x04\x10 ARM7 ; reg32,reg32 \x18\x04\x10 ARM7
; reg32,reg32,imm32 \x19\x04\x10 ARM7 ; reg32,reg32,imm32 \x19\x04\x10 ARM7
@ -208,22 +211,24 @@ reg32,memam2 \x17\x05\x10 ARM7
; reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7 ; reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7
[LDRHcc] [LDRHcc]
reg32,imm32 \x22\x50\xB0 ARM7 reg32,memam2 \x22\x10\xB0 ARM7
reg32,reg32 \x23\x50\xB0 ARM7 ;reg32,imm32 \x22\x50\xB0 ARM7
reg32,reg32,imm32 \x24\x50\xB0 ARM7 ;reg32,reg32 \x23\x50\xB0 ARM7
reg32,reg32,reg32 \x25\x10\xB0 ARM7 ;reg32,reg32,imm32 \x24\x50\xB0 ARM7
;reg32,reg32,reg32 \x25\x10\xB0 ARM7
[LDRSBcc] [LDRSBcc]
reg32,imm32 \x22\x50\xD0 ARM7 reg32,memam2 \x22\x10\xD0 ARM7
reg32,reg32 \x23\x50\xD0 ARM7 reg32,reg32 \x23\x50\xD0 ARM7
reg32,reg32,imm32 \x24\x50\xD0 ARM7 reg32,reg32,imm32 \x24\x50\xD0 ARM7
reg32,reg32,reg32 \x25\x10\xD0 ARM7 reg32,reg32,reg32 \x25\x10\xD0 ARM7
[LDRSHcc] [LDRSHcc]
reg32,imm32 \x22\x50\xF0 ARM7 reg32,memam2 \x22\x10\xF0 ARM7
reg32,reg32 \x23\x50\xF0 ARM7 ;reg32,imm32 \x22\x50\xF0 ARM7
reg32,reg32,imm32 \x24\x50\xF0 ARM7 ;reg32,reg32 \x23\x50\xF0 ARM7
reg32,reg32,reg32 \x25\x10\xF0 ARM7 ;reg32,reg32,imm32 \x24\x50\xF0 ARM7
;reg32,reg32,reg32 \x25\x10\xF0 ARM7
[LDRTcc] [LDRTcc]
@ -243,11 +248,10 @@ reg32,imm8,fpureg \xF0\x02\x01 FPA
reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7 reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
[MOVcc] [MOVcc]
; reg32,shifterop \x8\x0\0xd ARM7 reg32,shifterop \x8\x1\xA0 ARM7
; reg32,immshifter \x8\x0\0xd ARM7
; reg32,reg32,reg32 \x9\x1\xA0 ARM7 ; reg32,reg32,reg32 \x9\x1\xA0 ARM7
; reg32,reg32,imm \xA\x1\xA0 ARM7 reg32,reg32,shifterop \xA\x1\xA0 ARM7
; reg32,imm \xB\x3\xA0 ARM7 reg32,immshifter \xB\x1\xA0 ARM7
[MRC] [MRC]
; reg32,reg32 \321\301\1\x13\110 ARM7 ; reg32,reg32 \321\301\1\x13\110 ARM7
@ -272,18 +276,18 @@ fpureg,fpureg \xF2 FPA
fpureg,immfpu \xF2 FPA fpureg,immfpu \xF2 FPA
[MVNcc] [MVNcc]
; reg32,reg32 \x8\x0\0xf ARM7 reg32,reg32 \x8\x1\xE0 ARM7
; reg32,reg32,reg32 \x9\x1\xE0 ARM7 ; reg32,reg32,reg32 \x9\x1\xE0 ARM7
; reg32,reg32,imm \xA\x1\xE0 ARM7 reg32,reg32,shifterop \xA\x1\xE0 ARM7
; reg32,imm \xB\x3\xE0 ARM7 reg32,immshifter \xB\x1\xE0 ARM7
[NOP] [NOP]
[ORRcc] [ORRcc]
reg32,reg32,reg32 \4\x1\x80 ARM7 reg32,reg32,reg32 \4\x1\x80 ARM7
reg32,reg32,reg32,reg32 \5\x1\x80 ARM7 reg32,reg32,reg32,reg32 \5\x1\x80 ARM7
reg32,reg32,reg32,imm \6\x1\x80 ARM7 reg32,reg32,reg32,shifterop \6\x1\x80 ARM7
reg32,reg32,imm \7\x3\x80 ARM7 reg32,reg32,immshifter \7\x3\x80 ARM7
[RDFcc] [RDFcc]
@ -296,16 +300,16 @@ reg32,reg32,imm \7\x3\x80 ARM7
[RPWcc] [RPWcc]
[RSBcc] [RSBcc]
reg32,reg32,reg32 \4\x0\x60 ARM7 ;reg32,reg32,reg32 \4\x0\x60 ARM7
reg32,reg32,reg32,reg32 \5\x0\x60 ARM7 ;reg32,reg32,reg32,reg32 \5\x0\x60 ARM7
reg32,reg32,reg32,imm \6\x0\x60 ARM7 reg32,reg32,reg32,shifterop \6\x0\x60 ARM7
reg32,reg32,imm \7\x2\x60 ARM7 reg32,reg32,immshifter \7\x0\x60 ARM7
[RSCcc] [RSCcc]
reg32,reg32,reg32 \4\x0\xE0 ARM7 reg32,reg32,reg32 \4\x0\xE0 ARM7
reg32,reg32,reg32,reg32 \5\x0\xE0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xE0 ARM7
reg32,reg32,reg32,imm \6\x0\xE0 ARM7 reg32,reg32,reg32,imm \6\x0\xE0 ARM7
reg32,reg32,imm \7\x2\xE0 ARM7 reg32,reg32,immshifter \7\x2\xE0 ARM7
[RSFcc] [RSFcc]
@ -317,7 +321,7 @@ reg32,reg32,imm \7\x2\xE0 ARM7
reg32,reg32,reg32 \4\x0\xC0 ARM7 reg32,reg32,reg32 \4\x0\xC0 ARM7
reg32,reg32,reg32,reg32 \5\x0\xC0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xC0 ARM7
reg32,reg32,reg32,imm \6\x0\xC0 ARM7 reg32,reg32,reg32,imm \6\x0\xC0 ARM7
reg32,reg32,imm \7\x2\xC0 ARM7 reg32,reg32,immshifter \7\x2\xC0 ARM7
[SFMcc] [SFMcc]
reg32,imm8,fpureg \xF0\x02\x00 FPA reg32,imm8,fpureg \xF0\x02\x00 FPA
@ -338,6 +342,7 @@ reg32,reg32,reg32,reg32 \x16\x00\xC0\x90 ARM7
[STMcc] [STMcc]
memam4,reglist \x26\x80 ARM7 memam4,reglist \x26\x80 ARM7
reg32,reglist \x26\x80 ARM7
[STRcc] [STRcc]
reg32,memam2 \x17\x04\x00 ARM7 reg32,memam2 \x17\x04\x00 ARM7
@ -348,16 +353,17 @@ reg32,memam2 \x17\x04\x00 ARM7
; reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7 ; reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7
[STRBcc] [STRBcc]
reg32,memam2 \x17\x06\x00 ARM7 reg32,memam2 \x17\x04\x40 ARM7
[STRBTcc] [STRBTcc]
; A dummy since it is parsed as STR{cond}H ; A dummy since it is parsed as STR{cond}H
[STRHcc] [STRHcc]
reg32,imm32 \x22\x40\xB0 ARM7 reg32,memam2 \x22\x00\xB0 ARM7
reg32,reg32 \x23\x40\xB0 ARM7 ;reg32,imm32 \x22\x40\xB0 ARM7
reg32,reg32,imm32 \x24\x40\xB0 ARM7 ;reg32,reg32 \x23\x40\xB0 ARM7
reg32,reg32,reg32 \x25\x00\xB0 ARM7 ;reg32,reg32,imm32 \x24\x40\xB0 ARM7
;reg32,reg32,reg32 \x25\x00\xB0 ARM7
[STRTcc] [STRTcc]
@ -366,17 +372,17 @@ reg32,reg32,shifterop \4\x0\x40 ARM7
reg32,reg32,immshifter \4\x0\x40 ARM7 reg32,reg32,immshifter \4\x0\x40 ARM7
reg32,reg32,reg32 \4\x0\x40 ARM7 reg32,reg32,reg32 \4\x0\x40 ARM7
; reg32,reg32,reg32,reg32 \5\x0\x40 ARM7 ; reg32,reg32,reg32,reg32 \5\x0\x40 ARM7
; reg32,reg32,reg32,imm \6\x0\x40 ARM7 reg32,reg32,reg32,shifterop \6\x0\x40 ARM7
; reg32,reg32,imm \7\x2\x40 ARM7 ; reg32,reg32,imm \7\x2\x40 ARM7
[SWIcc] [SWIcc]
imm \2\x0F ARM7 imm \2\x0F ARM7
[SWPcc] [SWPcc]
reg32,reg32,reg32 \x27\x01\x90 ARM7 reg32,reg32,memam2 \x27\x10\x09 ARM7
[SWPBcc] [SWPBcc]
reg32,reg32,reg32 \x27\x01\x90 ARM7 reg32,reg32,reg32 \x27\x14\x09 ARM7
[TANcc] [TANcc]
@ -389,8 +395,8 @@ reg32,imm \xF\x3\x20 ARM7
[TSTcc] [TSTcc]
reg32,reg32 \xC\x1\x00 ARM7 reg32,reg32 \xC\x1\x00 ARM7
reg32,reg32,reg32 \xD\x1\x00 ARM7 reg32,reg32,reg32 \xD\x1\x00 ARM7
reg32,reg32,imm \xE\x1\x00 ARM7 reg32,reg32,shifterop \xE\x1\x00 ARM7
reg32,imm \xF\x3\x00 ARM7 reg32,immshifter \xF\x3\x00 ARM7
[UMLALcc] [UMLALcc]
reg32,reg32,reg32,reg32 \x16\x00\xA0\x90 ARM7 reg32,reg32,reg32,reg32 \x16\x00\xA0\x90 ARM7

2
compiler/arm/armnop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat } { don't edit, this file is generated from armins.dat }
105; 98;

245
compiler/arm/armtab.inc
View File

@ -31,7 +31,7 @@
( (
opcode : A_ADC; opcode : A_ADC;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#160; code : #7#2#160;
flags : if_arm7 flags : if_arm7
), ),
@ -52,14 +52,14 @@
( (
opcode : A_ADD; opcode : A_ADD;
ops : 4; ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #6#0#128; code : #6#0#128;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_ADD; opcode : A_ADD;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#128; code : #7#2#128;
flags : if_arm7 flags : if_arm7
), ),
@ -73,21 +73,14 @@
( (
opcode : A_AND; opcode : A_AND;
ops : 4; ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #5#0#0;
flags : if_arm7
),
(
opcode : A_AND;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
code : #6#0#0; code : #6#0#0;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_AND; opcode : A_AND;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#0; code : #7#2#0;
flags : if_arm7 flags : if_arm7
), ),
@ -108,28 +101,7 @@
( (
opcode : A_BIC; opcode : A_BIC;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #4#1#192;
flags : if_arm7
),
(
opcode : A_BIC;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
code : #5#1#192;
flags : if_arm7
),
(
opcode : A_BIC;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
code : #6#1#192;
flags : if_arm7
),
(
opcode : A_BIC;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
code : #7#3#192; code : #7#3#192;
flags : if_arm7 flags : if_arm7
), ),
@ -199,8 +171,8 @@
( (
opcode : A_CMN; opcode : A_CMN;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate,ot_none,ot_none); optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
code : #15#3#96; code : #15#1#96;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -220,14 +192,14 @@
( (
opcode : A_CMP; opcode : A_CMP;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none);
code : #14#1#64; code : #14#1#64;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_CMP; opcode : A_CMP;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate,ot_none,ot_none); optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
code : #15#3#64; code : #15#3#64;
flags : if_arm7 flags : if_arm7
), ),
@ -248,21 +220,14 @@
( (
opcode : A_EOR; opcode : A_EOR;
ops : 4; ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #5#0#32;
flags : if_arm7
),
(
opcode : A_EOR;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
code : #6#0#32; code : #6#0#32;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_EOR; opcode : A_EOR;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#32; code : #7#2#32;
flags : if_arm7 flags : if_arm7
), ),
@ -280,53 +245,39 @@
code : #38#129; code : #38#129;
flags : if_arm7 flags : if_arm7
), ),
(
opcode : A_LDM;
ops : 2;
optypes : (ot_reg32,ot_reglist,ot_none,ot_none);
code : #38#129;
flags : if_arm7
),
( (
opcode : A_LDRB; opcode : A_LDRB;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #23#7#16; code : #23#4#80;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_LDR; opcode : A_LDR;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #23#5#16; code : #23#4#16;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_LDRH; opcode : A_LDRH;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #34#80#176; code : #34#16#176;
flags : if_arm7
),
(
opcode : A_LDRH;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #35#80#176;
flags : if_arm7
),
(
opcode : A_LDRH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
code : #36#80#176;
flags : if_arm7
),
(
opcode : A_LDRH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
code : #37#16#176;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_LDRSB; opcode : A_LDRSB;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #34#80#208; code : #34#16#208;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -353,29 +304,8 @@
( (
opcode : A_LDRSH; opcode : A_LDRSH;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #34#80#240; code : #34#16#240;
flags : if_arm7
),
(
opcode : A_LDRSH;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #35#80#240;
flags : if_arm7
),
(
opcode : A_LDRSH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
code : #36#80#240;
flags : if_arm7
),
(
opcode : A_LDRSH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
code : #37#16#240;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -392,6 +322,27 @@
code : #21#0#32#144; code : #21#0#32#144;
flags : if_arm7 flags : if_arm7
), ),
(
opcode : A_MOV;
ops : 2;
optypes : (ot_reg32,ot_shifterop,ot_none,ot_none);
code : #8#1#160;
flags : if_arm7
),
(
opcode : A_MOV;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none);
code : #10#1#160;
flags : if_arm7
),
(
opcode : A_MOV;
ops : 2;
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
code : #11#1#160;
flags : if_arm7
),
( (
opcode : A_MRS; opcode : A_MRS;
ops : 2; ops : 2;
@ -441,6 +392,27 @@
code : #242; code : #242;
flags : if_fpa flags : if_fpa
), ),
(
opcode : A_MVN;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #8#1#224;
flags : if_arm7
),
(
opcode : A_MVN;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none);
code : #10#1#224;
flags : if_arm7
),
(
opcode : A_MVN;
ops : 2;
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
code : #11#1#224;
flags : if_arm7
),
( (
opcode : A_ORR; opcode : A_ORR;
ops : 3; ops : 3;
@ -458,43 +430,29 @@
( (
opcode : A_ORR; opcode : A_ORR;
ops : 4; ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #6#1#128; code : #6#1#128;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_ORR; opcode : A_ORR;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#3#128; code : #7#3#128;
flags : if_arm7 flags : if_arm7
), ),
(
opcode : A_RSB;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
code : #4#0#96;
flags : if_arm7
),
( (
opcode : A_RSB; opcode : A_RSB;
ops : 4; ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #5#0#96;
flags : if_arm7
),
(
opcode : A_RSB;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
code : #6#0#96; code : #6#0#96;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_RSB; opcode : A_RSB;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#96; code : #7#0#96;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -521,7 +479,7 @@
( (
opcode : A_RSC; opcode : A_RSC;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#224; code : #7#2#224;
flags : if_arm7 flags : if_arm7
), ),
@ -549,7 +507,7 @@
( (
opcode : A_SBC; opcode : A_SBC;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
code : #7#2#192; code : #7#2#192;
flags : if_arm7 flags : if_arm7
), ),
@ -581,6 +539,13 @@
code : #38#128; code : #38#128;
flags : if_arm7 flags : if_arm7
), ),
(
opcode : A_STM;
ops : 2;
optypes : (ot_reg32,ot_reglist,ot_none,ot_none);
code : #38#128;
flags : if_arm7
),
( (
opcode : A_STR; opcode : A_STR;
ops : 2; ops : 2;
@ -592,35 +557,14 @@
opcode : A_STRB; opcode : A_STRB;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #23#6#0; code : #23#4#64;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_STRH; opcode : A_STRH;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none); optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
code : #34#64#176; code : #34#0#176;
flags : if_arm7
),
(
opcode : A_STRH;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #35#64#176;
flags : if_arm7
),
(
opcode : A_STRH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
code : #36#64#176;
flags : if_arm7
),
(
opcode : A_STRH;
ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
code : #37#0#176;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -644,6 +588,13 @@
code : #4#0#64; code : #4#0#64;
flags : if_arm7 flags : if_arm7
), ),
(
opcode : A_SUB;
ops : 4;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop);
code : #6#0#64;
flags : if_arm7
),
( (
opcode : A_SWI; opcode : A_SWI;
ops : 1; ops : 1;
@ -654,15 +605,15 @@
( (
opcode : A_SWP; opcode : A_SWP;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none); optypes : (ot_reg32,ot_reg32,ot_memoryam2,ot_none);
code : #39#1#144; code : #39#16#9;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_SWPB; opcode : A_SWPB;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none); optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
code : #39#1#144; code : #39#20#9;
flags : if_arm7 flags : if_arm7
), ),
( (
@ -710,14 +661,14 @@
( (
opcode : A_TST; opcode : A_TST;
ops : 3; ops : 3;
optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none); optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none);
code : #14#1#0; code : #14#1#0;
flags : if_arm7 flags : if_arm7
), ),
( (
opcode : A_TST; opcode : A_TST;
ops : 2; ops : 2;
optypes : (ot_reg32,ot_immediate,ot_none,ot_none); optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
code : #15#3#0; code : #15#3#0;
flags : if_arm7 flags : if_arm7
), ),

12
compiler/ogcoff.pas
View File

@ -1009,10 +1009,9 @@ const pemagic : array[0..3] of byte = (
result:=aname result:=aname
else else
begin begin
{ non-PECOFF targets lack rodata support. { non-PECOFF targets lack rodata support }
TODO: WinCE likely supports it, but needs testing. }
if (atype in [sec_rodata,sec_rodata_norel]) and if (atype in [sec_rodata,sec_rodata_norel]) and
not (target_info.system in systems_windows) then not (target_info.system in systems_all_windows) then
atype:=sec_data; atype:=sec_data;
secname:=coffsecnames[atype]; secname:=coffsecnames[atype];
if create_smartlink_sections and if create_smartlink_sections and
@ -1038,8 +1037,7 @@ const pemagic : array[0..3] of byte = (
begin begin
if (aType in [sec_rodata,sec_rodata_norel]) then if (aType in [sec_rodata,sec_rodata_norel]) then
begin begin
{ TODO: WinCE needs testing } if (target_info.system in systems_all_windows) then
if (target_info.system in systems_windows) then
aType:=sec_rodata_norel aType:=sec_rodata_norel
else else
aType:=sec_data; aType:=sec_data;
@ -1279,6 +1277,8 @@ const pemagic : array[0..3] of byte = (
rel.reloctype:=IMAGE_REL_ARM_ADDR32NB; rel.reloctype:=IMAGE_REL_ARM_ADDR32NB;
RELOC_SECREL32 : RELOC_SECREL32 :
rel.reloctype:=IMAGE_REL_ARM_SECREL; rel.reloctype:=IMAGE_REL_ARM_SECREL;
RELOC_RELATIVE_24 :
rel.reloctype:=IMAGE_REL_ARM_BRANCH24;
{$endif arm} {$endif arm}
{$ifdef i386} {$ifdef i386}
RELOC_RELATIVE : RELOC_RELATIVE :
@ -3045,7 +3045,7 @@ const pemagic : array[0..3] of byte = (
asmbin : ''; asmbin : '';
asmcmd : ''; asmcmd : '';
supported_targets : [system_arm_wince]; supported_targets : [system_arm_wince];
flags : [af_outputbinary]; flags : [af_outputbinary,af_smartlink_sections];
labelprefix : '.L'; labelprefix : '.L';
comment : ''; comment : '';
dollarsign: '$'; dollarsign: '$';