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* MIPS: handle 8 and 16-bit arithmetic shifts internally, by shifting argument left by 24/16 bits, followed with 32-bit arithmetic shift right by appropriately adjusted amount.

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This approach should be usable for other non-x86 targets as well.

git-svn-id: trunk@25062 -
This commit is contained in:
sergei 2013-07-08 08:45:16 +00:00
parent 87a0868606
commit 9e4cc57768
2 changed files with 28 additions and 4 deletions
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26
compiler/mips/cgcpu.pas
View File

@ -803,9 +803,24 @@ end;
procedure TCGMIPS.a_op_reg_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister); procedure TCGMIPS.a_op_reg_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
var
hreg: tregister;
begin begin
if (TOpcg2AsmOp[op]=A_NONE) then if (TOpcg2AsmOp[op]=A_NONE) then
InternalError(2013070305); InternalError(2013070305);
if (op=OP_SAR) then
begin
if (size in [OS_S8,OS_S16]) then
begin
{ Shift left by 16/24 bits and increase amount of right shift by same value }
list.concat(taicpu.op_reg_reg_const(A_SLL, dst, src2, 32-(tcgsize2size[size]*8)));
hreg:=GetIntRegister(list,OS_INT);
a_op_const_reg_reg(list,OP_ADD,OS_INT,32-(tcgsize2size[size]*8),src1,dst);
src1:=hreg;
end
else if not (size in [OS_32,OS_S32]) then
InternalError(2013070306);
end;
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op], dst, src2, src1)); list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op], dst, src2, src1));
maybeadjustresult(list,op,size,dst); maybeadjustresult(list,op,size,dst);
end; end;
@ -885,8 +900,17 @@ begin
list.concat(taicpu.op_reg_reg_const(A_SRL,dst,src,a)); list.concat(taicpu.op_reg_reg_const(A_SRL,dst,src,a));
OP_SAR: OP_SAR:
begin
if (size in [OS_S8,OS_S16]) then
begin
list.concat(taicpu.op_reg_reg_const(A_SLL,dst,src,32-(tcgsize2size[size]*8)));
inc(a,32-tcgsize2size[size]*8);
src:=dst;
end
else if not (size in [OS_32,OS_S32]) then
InternalError(2013070303);
list.concat(taicpu.op_reg_reg_const(A_SRA,dst,src,a)); list.concat(taicpu.op_reg_reg_const(A_SRA,dst,src,a));
end;
else else
internalerror(2007012601); internalerror(2007012601);
end; end;

4
rtl/inc/systemh.inc
View File

@ -861,10 +861,10 @@ function RolQWord(Const AValue : QWord;const Dist : Byte): QWord;{$ifdef SYSTEMI
{$ifdef FPC_HAS_INTERNAL_SAR} {$ifdef FPC_HAS_INTERNAL_SAR}
{$if defined(cpux86_64) or defined(cpui386)} {$if defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)}
{$define FPC_HAS_INTERNAL_SAR_BYTE} {$define FPC_HAS_INTERNAL_SAR_BYTE}
{$define FPC_HAS_INTERNAL_SAR_WORD} {$define FPC_HAS_INTERNAL_SAR_WORD}
{$endif defined(cpux86_64) or defined(cpui386)} {$endif defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)}
{ currently, all supported CPUs have an internal 32 bit sar implementation } { currently, all supported CPUs have an internal 32 bit sar implementation }
{ $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(mips) or defined(mipsel)} { $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(mips) or defined(mipsel)}