From 9eab90d8c4b415190cebbe710b4772e31d20e4de Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Sat, 21 Feb 2015 21:58:30 +0000
Subject: [PATCH] * always pass the architecture to the arm assembler * encode
 pld/ldrd in arm.inc using .long, so it causes no errors with older
 architectures settings of the assembler

git-svn-id: trunk@29780 -
---
 compiler/arm/agarmgas.pas |  3 +--
 rtl/arm/arm.inc           | 27 ++++++++++++++++++++-------
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/compiler/arm/agarmgas.pas b/compiler/arm/agarmgas.pas
index 0ac95122c9..666ce49bf6 100644
--- a/compiler/arm/agarmgas.pas
+++ b/compiler/arm/agarmgas.pas
@@ -114,8 +114,7 @@ unit agarmgas;
           result:='-march='+cputype_to_gas_march[current_settings.cputype]+' -mthumb -mthumb-interwork '+result
         else if GenerateThumbCode then
           result:='-march='+cputype_to_gas_march[current_settings.cputype]+' -mthumb -mthumb-interwork '+result
-        // EDSP instructions in RTL require armv5te at least to not generate error
-        else if current_settings.cputype >= cpu_armv5te then
+        else
           result:='-march='+cputype_to_gas_march[current_settings.cputype]+' '+result;
 
         if target_info.abi = abi_eabihf then
diff --git a/rtl/arm/arm.inc b/rtl/arm/arm.inc
index 61051abb50..bdc65e47e1 100644
--- a/rtl/arm/arm.inc
+++ b/rtl/arm/arm.inc
@@ -217,7 +217,10 @@ procedure Move(const source;var dest;count:longint);[public, alias: 'FPC_MOVE'];
 procedure Move_pld(const source;var dest;count:longint);assembler;nostackframe;
 {$endif CPUARM_HAS_EDSP}
 asm
-  pld [r0]
+  // pld [r0]
+  // encode this using .long so the rtl assembles also with instructions sets not supporting pld
+  .long 0xf5d0f000
+
   // count <=0 ?
   cmp r2,#0
 {$ifdef CPUARM_HAS_BX}
@@ -237,11 +240,18 @@ asm
   tsteq r1, #3         //    (dest and 3) <> 0 then
   bne   .Lbyteloop     //   DoForwardByteCopy;
 
-  pld   [r0,#32]
+  // pld   [r0,#32]
+  // encode this using .long so the rtl assembles also with instructions sets not supporting pld
+  .long 0xf5d0f020
+
 .Ldwordloop:
   ldmia r0!, {r3, ip}
+
   // preload
-  pld   [r0,#64]
+  // pld   [r0,#64]
+  // encode this using .long so the rtl assembles also with instructions sets not supporting pld
+  .long 0xf5d0f040
+
   sub   r2,r2,#8
   cmp   r2, #8
   stmia r1!, {r3, ip}
@@ -526,11 +536,11 @@ asm
 {$endif}
   stmfd   sp!, {r1, lr}
   sub     r0, r1, #8
-{$ifdef CPUARM_HAS_BLX}
+{$if defined(CPUARM_HAS_BX) and not(defined(WINCE))}
   blx     InterLockedDecrement
-{$else}
+{$else defined(CPUARM_HAS_BX) and not(defined(WINCE))}
   bl      InterLockedDecrement
-{$endif}
+{$endif defined(CPUARM_HAS_BX) and not(defined(WINCE))}
   // InterLockedDecrement is a nice guy and sets the z flag for us
   // if the reference count dropped to 0
   ldmnefd sp!, {r1, pc}
@@ -962,7 +972,10 @@ begin
   in_edsp_test:=true;
   asm
     bic r0,sp,#7
-    ldrd r0,r1,[r0]
+
+    // ldrd r0,r1,[r0]
+    // encode this using .long so the rtl assembles also with instructions sets not supporting pld
+    .long 0xe1c000d0
   end;
   in_edsp_test:=false;
   if cpu_has_edsp then