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https://gitlab.com/freepascal.org/fpc/source.git
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* some x86-64 compilation fixe
This commit is contained in:
florian
parent
d84b7d0743
commit
9fd5217032
@ -1718,16 +1718,16 @@ implementation
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initfputype:=fpu_fpa;
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{$endif arm}
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{$ifdef x86_64}
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initoptprocessor:=ClassDefault;
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initspecificoptprocessor:=ClassDefault;
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initoptprocessor:=ClassAthlon64;
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initspecificoptprocessor:=ClassAthlon64;
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initfputype:=fpu_standard;
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initfputype:=fpu_sse2;
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initpackenum:=4;
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{$IFDEF testvarsets}
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initsetalloc:=0;
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{$ENDIF}
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initasmmode:=asmmode_direct;
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initasmmode:=asmmode_x8664_gas;
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{$endif x86_64}
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initinterfacetype:=it_interfacecom;
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initdefproccall:=pocall_default;
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@ -1744,7 +1744,10 @@ implementation
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end.
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{
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$Log$
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Revision 1.116 2003-11-30 19:35:29 florian
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Revision 1.117 2003-12-20 12:38:51 florian
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* some x86-64 compilation fixe
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Revision 1.116 2003/11/30 19:35:29 florian
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* fixed several arm related problems
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Revision 1.115 2003/11/12 16:05:39 florian
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@ -2460,6 +2460,11 @@ type
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if (procdefinition.proccalloption=pocall_inline) then
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begin
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current_procinfo.flags:=current_procinfo.flags+((procdefinition as tprocdef).inlininginfo^.flags*inherited_inlining_flags);
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{
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writeln(longint(current_procinfo.flags));
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writeln(longint(inherited_inlining_flags));
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writeln(longint((procdefinition as tprocdef).inlininginfo^.flags));
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}
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if assigned(methodpointer) then
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CGMessage(cg_e_unable_inline_object_methods);
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if assigned(right) then
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@ -2699,7 +2704,10 @@ begin
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end.
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{
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$Log$
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Revision 1.214 2003-12-16 22:09:31 florian
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Revision 1.215 2003-12-20 12:38:51 florian
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* some x86-64 compilation fixe
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Revision 1.214 2003/12/16 22:09:31 florian
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* better inheritence of procinfo flags of inlined procedures
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Revision 1.213 2003/12/16 21:29:24 florian
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@ -72,6 +72,7 @@ interface
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,asmmode_ppc_motorola
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,asmmode_arm_gas
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,asmmode_sparc_gas
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,asmmode_x8664_gas
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);
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(* IMPORTANT NOTE:
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@ -649,7 +650,10 @@ finalization
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end.
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{
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$Log$
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Revision 1.74 2003-11-29 15:53:06 florian
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Revision 1.75 2003-12-20 12:38:51 florian
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* some x86-64 compilation fixe
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Revision 1.74 2003/11/29 15:53:06 florian
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+ nasmelf mode for BeOS
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+ DQWORD directive in intel assembler mode
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@ -26,6 +26,9 @@ Unit cpuinfo;
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Interface
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uses
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globtype;
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Type
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AWord = QWord;
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PAWord = ^AWord;
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@ -52,17 +55,12 @@ Type
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tprocessors =
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(no_processor,
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ClassDefault
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ClassAthlon64
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);
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tfputype =
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(no_fpuprocessor,
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fpu_soft,
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fpu_standard,
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fpu_x87,
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fpu_sse,
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fpu_sse2,
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fpu_sse3
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fpu_sse2
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);
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Const
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@ -82,12 +80,36 @@ Const
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jmp_buf_size = 48;
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{ calling conventions supported by the code generator }
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supported_calling_conventions = [
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pocall_internproc,
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pocall_compilerproc,
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pocall_inline,
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pocall_register,
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pocall_safecall,
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pocall_stdcall,
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pocall_cdecl,
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pocall_cppdecl
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];
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processorsstr : array[tprocessors] of string[10] = ('',
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'ATHLON64'
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);
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fputypestr : array[tfputype] of string[6] = ('',
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'SSE2'
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);
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Implementation
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end.
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{
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$Log$
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Revision 1.7 2003-09-24 17:12:02 florian
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Revision 1.8 2003-12-20 12:38:51 florian
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* some x86-64 compilation fixe
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Revision 1.7 2003/09/24 17:12:02 florian
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* several fixes for new reg allocator
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Revision 1.6 2003/01/05 13:36:54 florian
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@ -1,124 +1,124 @@
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{ don't edit, this file is generated from x86reg.dat }
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NR_NO = $00000000;
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NR_AL = $01010000;
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NR_AH = $01020000;
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NR_AX = $01030000;
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NR_EAX = $01040000;
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NR_RAX = $01050000;
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NR_CL = $01010001;
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NR_CH = $01020001;
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NR_CX = $01030001;
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NR_ECX = $01040001;
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NR_RCX = $01050001;
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NR_DL = $01010002;
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NR_DH = $01020002;
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NR_DX = $01030002;
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NR_EDX = $01040002;
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NR_RDX = $01050002;
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NR_BL = $01010003;
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NR_BH = $01020003;
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NR_BX = $01030003;
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NR_EBX = $01040003;
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NR_RBX = $01050003;
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NR_SIL = $01010004;
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NR_SI = $01030004;
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NR_ESI = $01040004;
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NR_RSI = $01050004;
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NR_DIL = $01010005;
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NR_DI = $01030005;
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NR_EDI = $01040005;
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NR_RDI = $01050005;
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NR_BPL = $01010006;
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NR_BP = $01030006;
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NR_EBP = $01040006;
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NR_RBP = $01050006;
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NR_SPL = $01010007;
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NR_SP = $01030007;
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NR_ESP = $01040007;
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NR_RSP = $01050007;
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NR_R8 = $01050008;
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NR_R8L = $01010008;
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NR_R8W = $01030008;
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NR_R8D = $01040008;
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NR_R9 = $01050009;
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NR_R9L = $01010009;
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NR_R9W = $01030009;
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NR_R9D = $01040009;
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NR_R10 = $0105000a;
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NR_R10L = $0101000a;
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NR_R10W = $0103000a;
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NR_R10D = $0104000a;
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NR_R11 = $0105000b;
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NR_R11L = $0101000b;
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NR_R11W = $0103000b;
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NR_R11D = $0104000b;
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NR_R12 = $0105000c;
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NR_R12L = $0101000c;
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NR_R12W = $0103000c;
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NR_R12D = $0104000c;
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NR_R13 = $0105000d;
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NR_R13L = $0101000d;
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NR_R13W = $0103000d;
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NR_R13D = $0104000d;
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NR_R14 = $0105000e;
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NR_R14L = $0101000e;
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NR_R14W = $0103000e;
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NR_R14D = $0104000e;
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NR_R15 = $0105000f;
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NR_R15L = $0101000f;
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NR_R15W = $0103000f;
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NR_R15D = $0104000f;
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NR_CS = $05000001;
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NR_DS = $05000002;
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NR_ES = $05000003;
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NR_SS = $05000004;
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NR_FS = $05000005;
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NR_GS = $05000006;
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NR_DR0 = $05000007;
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NR_DR1 = $05000008;
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NR_DR2 = $05000009;
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NR_DR3 = $0500000a;
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NR_DR6 = $0500000b;
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NR_DR7 = $0500000c;
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NR_CR0 = $0500000d;
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NR_CR2 = $0500000e;
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NR_CR3 = $0500000f;
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NR_CR4 = $05000010;
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NR_TR3 = $05000011;
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NR_TR4 = $05000012;
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NR_TR5 = $05000013;
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NR_TR6 = $05000014;
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NR_TR7 = $05000015;
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NR_ST0 = $02000000;
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NR_ST1 = $02000001;
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NR_ST2 = $02000002;
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NR_ST3 = $02000003;
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NR_ST4 = $02000004;
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NR_ST5 = $02000005;
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NR_ST6 = $02000006;
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NR_ST7 = $02000007;
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NR_ST = $02000008;
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NR_MM0 = $03000000;
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NR_MM1 = $03000001;
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NR_MM2 = $03000002;
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NR_MM3 = $03000003;
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NR_MM4 = $03000004;
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NR_MM5 = $03000005;
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NR_MM6 = $03000006;
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NR_MM7 = $03000007;
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NR_XMM0 = $04000000;
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NR_XMM1 = $04000001;
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NR_XMM2 = $04000002;
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NR_XMM3 = $04000003;
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NR_XMM4 = $04000004;
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NR_XMM5 = $04000005;
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NR_XMM6 = $04000006;
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NR_XMM7 = $04000007;
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NR_XMM8 = $04000008;
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NR_XMM9 = $04000009;
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NR_XMM10 = $0400000a;
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NR_XMM11 = $0400000b;
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NR_XMM12 = $0400000c;
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NR_XMM13 = $0400000d;
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NR_XMM14 = $0400000e;
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NR_XMM15 = $0400000f;
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NR_NO = tregister($00000000);
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NR_AL = tregister($01010000);
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NR_AH = tregister($01020000);
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NR_AX = tregister($01030000);
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NR_EAX = tregister($01040000);
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NR_RAX = tregister($01050000);
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NR_CL = tregister($01010001);
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NR_CH = tregister($01020001);
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NR_CX = tregister($01030001);
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NR_ECX = tregister($01040001);
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NR_RCX = tregister($01050001);
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NR_DL = tregister($01010002);
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NR_DH = tregister($01020002);
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NR_DX = tregister($01030002);
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NR_EDX = tregister($01040002);
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NR_RDX = tregister($01050002);
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NR_BL = tregister($01010003);
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NR_BH = tregister($01020003);
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NR_BX = tregister($01030003);
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NR_EBX = tregister($01040003);
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NR_RBX = tregister($01050003);
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NR_SIL = tregister($01010004);
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NR_SI = tregister($01030004);
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NR_ESI = tregister($01040004);
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NR_RSI = tregister($01050004);
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NR_DIL = tregister($01010005);
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NR_DI = tregister($01030005);
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NR_EDI = tregister($01040005);
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NR_RDI = tregister($01050005);
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NR_BPL = tregister($01010006);
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NR_BP = tregister($01030006);
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NR_EBP = tregister($01040006);
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NR_RBP = tregister($01050006);
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NR_SPL = tregister($01010007);
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NR_SP = tregister($01030007);
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NR_ESP = tregister($01040007);
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NR_RSP = tregister($01050007);
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NR_R8 = tregister($01050008);
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NR_R8L = tregister($01010008);
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NR_R8W = tregister($01030008);
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NR_R8D = tregister($01040008);
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NR_R9 = tregister($01050009);
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NR_R9L = tregister($01010009);
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NR_R9W = tregister($01030009);
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NR_R9D = tregister($01040009);
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NR_R10 = tregister($0105000a);
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NR_R10L = tregister($0101000a);
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NR_R10W = tregister($0103000a);
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NR_R10D = tregister($0104000a);
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NR_R11 = tregister($0105000b);
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NR_R11L = tregister($0101000b);
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NR_R11W = tregister($0103000b);
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NR_R11D = tregister($0104000b);
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NR_R12 = tregister($0105000c);
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NR_R12L = tregister($0101000c);
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NR_R12W = tregister($0103000c);
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NR_R12D = tregister($0104000c);
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NR_R13 = tregister($0105000d);
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NR_R13L = tregister($0101000d);
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NR_R13W = tregister($0103000d);
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NR_R13D = tregister($0104000d);
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NR_R14 = tregister($0105000e);
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NR_R14L = tregister($0101000e);
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NR_R14W = tregister($0103000e);
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NR_R14D = tregister($0104000e);
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NR_R15 = tregister($0105000f);
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NR_R15L = tregister($0101000f);
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NR_R15W = tregister($0103000f);
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NR_R15D = tregister($0104000f);
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NR_CS = tregister($05000001);
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NR_DS = tregister($05000002);
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NR_ES = tregister($05000003);
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NR_SS = tregister($05000004);
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NR_FS = tregister($05000005);
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NR_GS = tregister($05000006);
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NR_DR0 = tregister($05000007);
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NR_DR1 = tregister($05000008);
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NR_DR2 = tregister($05000009);
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NR_DR3 = tregister($0500000a);
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NR_DR6 = tregister($0500000b);
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NR_DR7 = tregister($0500000c);
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NR_CR0 = tregister($0500000d);
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NR_CR2 = tregister($0500000e);
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NR_CR3 = tregister($0500000f);
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NR_CR4 = tregister($05000010);
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NR_TR3 = tregister($05000011);
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NR_TR4 = tregister($05000012);
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NR_TR5 = tregister($05000013);
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NR_TR6 = tregister($05000014);
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NR_TR7 = tregister($05000015);
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NR_ST0 = tregister($02000000);
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NR_ST1 = tregister($02000001);
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NR_ST2 = tregister($02000002);
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NR_ST3 = tregister($02000003);
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NR_ST4 = tregister($02000004);
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NR_ST5 = tregister($02000005);
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NR_ST6 = tregister($02000006);
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NR_ST7 = tregister($02000007);
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NR_ST = tregister($02000008);
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NR_MM0 = tregister($03000000);
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NR_MM1 = tregister($03000001);
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NR_MM2 = tregister($03000002);
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NR_MM3 = tregister($03000003);
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NR_MM4 = tregister($03000004);
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NR_MM5 = tregister($03000005);
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NR_MM6 = tregister($03000006);
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NR_MM7 = tregister($03000007);
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NR_XMM0 = tregister($04000000);
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NR_XMM1 = tregister($04000001);
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NR_XMM2 = tregister($04000002);
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NR_XMM3 = tregister($04000003);
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NR_XMM4 = tregister($04000004);
|
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NR_XMM5 = tregister($04000005);
|
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NR_XMM6 = tregister($04000006);
|
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NR_XMM7 = tregister($04000007);
|
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NR_XMM8 = tregister($04000008);
|
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NR_XMM9 = tregister($04000009);
|
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NR_XMM10 = tregister($0400000a);
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NR_XMM11 = tregister($0400000b);
|
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NR_XMM12 = tregister($0400000c);
|
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NR_XMM13 = tregister($0400000d);
|
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NR_XMM14 = tregister($0400000e);
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NR_XMM15 = tregister($0400000f);
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@ -1,124 +1,124 @@
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{ don't edit, this file is generated from x86reg.dat }
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$00000000,
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$01010000,
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$01020000,
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$01030000,
|
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$01040000,
|
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$01050000,
|
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$01010001,
|
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$01020001,
|
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$01030001,
|
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$01040001,
|
||||
$01050001,
|
||||
$01010002,
|
||||
$01020002,
|
||||
$01030002,
|
||||
$01040002,
|
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$01050002,
|
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$01010003,
|
||||
$01020003,
|
||||
$01030003,
|
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$01040003,
|
||||
$01050003,
|
||||
$01010004,
|
||||
$01030004,
|
||||
$01040004,
|
||||
$01050004,
|
||||
$01010005,
|
||||
$01030005,
|
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$01040005,
|
||||
$01050005,
|
||||
$01010006,
|
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$01030006,
|
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$01040006,
|
||||
$01050006,
|
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$01010007,
|
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$01030007,
|
||||
$01040007,
|
||||
$01050007,
|
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$01050008,
|
||||
$01010008,
|
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$01030008,
|
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$01040008,
|
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$01050009,
|
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$01010009,
|
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$01030009,
|
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$01040009,
|
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$0105000a,
|
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$0101000a,
|
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$0103000a,
|
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$0104000a,
|
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$0105000b,
|
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$0101000b,
|
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$0103000b,
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$0104000b,
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$0105000c,
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$0101000c,
|
||||
$0103000c,
|
||||
$0104000c,
|
||||
$0105000d,
|
||||
$0101000d,
|
||||
$0103000d,
|
||||
$0104000d,
|
||||
$0105000e,
|
||||
$0101000e,
|
||||
$0103000e,
|
||||
$0104000e,
|
||||
$0105000f,
|
||||
$0101000f,
|
||||
$0103000f,
|
||||
$0104000f,
|
||||
$05000001,
|
||||
$05000002,
|
||||
$05000003,
|
||||
$05000004,
|
||||
$05000005,
|
||||
$05000006,
|
||||
$05000007,
|
||||
$05000008,
|
||||
$05000009,
|
||||
$0500000a,
|
||||
$0500000b,
|
||||
$0500000c,
|
||||
$0500000d,
|
||||
$0500000e,
|
||||
$0500000f,
|
||||
$05000010,
|
||||
$05000011,
|
||||
$05000012,
|
||||
$05000013,
|
||||
$05000014,
|
||||
$05000015,
|
||||
$02000000,
|
||||
$02000001,
|
||||
$02000002,
|
||||
$02000003,
|
||||
$02000004,
|
||||
$02000005,
|
||||
$02000006,
|
||||
$02000007,
|
||||
$02000008,
|
||||
$03000000,
|
||||
$03000001,
|
||||
$03000002,
|
||||
$03000003,
|
||||
$03000004,
|
||||
$03000005,
|
||||
$03000006,
|
||||
$03000007,
|
||||
$04000000,
|
||||
$04000001,
|
||||
$04000002,
|
||||
$04000003,
|
||||
$04000004,
|
||||
$04000005,
|
||||
$04000006,
|
||||
$04000007,
|
||||
$04000008,
|
||||
$04000009,
|
||||
$0400000a,
|
||||
$0400000b,
|
||||
$0400000c,
|
||||
$0400000d,
|
||||
$0400000e,
|
||||
$0400000f
|
||||
tregister($00000000),
|
||||
tregister($01010000),
|
||||
tregister($01020000),
|
||||
tregister($01030000),
|
||||
tregister($01040000),
|
||||
tregister($01050000),
|
||||
tregister($01010001),
|
||||
tregister($01020001),
|
||||
tregister($01030001),
|
||||
tregister($01040001),
|
||||
tregister($01050001),
|
||||
tregister($01010002),
|
||||
tregister($01020002),
|
||||
tregister($01030002),
|
||||
tregister($01040002),
|
||||
tregister($01050002),
|
||||
tregister($01010003),
|
||||
tregister($01020003),
|
||||
tregister($01030003),
|
||||
tregister($01040003),
|
||||
tregister($01050003),
|
||||
tregister($01010004),
|
||||
tregister($01030004),
|
||||
tregister($01040004),
|
||||
tregister($01050004),
|
||||
tregister($01010005),
|
||||
tregister($01030005),
|
||||
tregister($01040005),
|
||||
tregister($01050005),
|
||||
tregister($01010006),
|
||||
tregister($01030006),
|
||||
tregister($01040006),
|
||||
tregister($01050006),
|
||||
tregister($01010007),
|
||||
tregister($01030007),
|
||||
tregister($01040007),
|
||||
tregister($01050007),
|
||||
tregister($01050008),
|
||||
tregister($01010008),
|
||||
tregister($01030008),
|
||||
tregister($01040008),
|
||||
tregister($01050009),
|
||||
tregister($01010009),
|
||||
tregister($01030009),
|
||||
tregister($01040009),
|
||||
tregister($0105000a),
|
||||
tregister($0101000a),
|
||||
tregister($0103000a),
|
||||
tregister($0104000a),
|
||||
tregister($0105000b),
|
||||
tregister($0101000b),
|
||||
tregister($0103000b),
|
||||
tregister($0104000b),
|
||||
tregister($0105000c),
|
||||
tregister($0101000c),
|
||||
tregister($0103000c),
|
||||
tregister($0104000c),
|
||||
tregister($0105000d),
|
||||
tregister($0101000d),
|
||||
tregister($0103000d),
|
||||
tregister($0104000d),
|
||||
tregister($0105000e),
|
||||
tregister($0101000e),
|
||||
tregister($0103000e),
|
||||
tregister($0104000e),
|
||||
tregister($0105000f),
|
||||
tregister($0101000f),
|
||||
tregister($0103000f),
|
||||
tregister($0104000f),
|
||||
tregister($05000001),
|
||||
tregister($05000002),
|
||||
tregister($05000003),
|
||||
tregister($05000004),
|
||||
tregister($05000005),
|
||||
tregister($05000006),
|
||||
tregister($05000007),
|
||||
tregister($05000008),
|
||||
tregister($05000009),
|
||||
tregister($0500000a),
|
||||
tregister($0500000b),
|
||||
tregister($0500000c),
|
||||
tregister($0500000d),
|
||||
tregister($0500000e),
|
||||
tregister($0500000f),
|
||||
tregister($05000010),
|
||||
tregister($05000011),
|
||||
tregister($05000012),
|
||||
tregister($05000013),
|
||||
tregister($05000014),
|
||||
tregister($05000015),
|
||||
tregister($02000000),
|
||||
tregister($02000001),
|
||||
tregister($02000002),
|
||||
tregister($02000003),
|
||||
tregister($02000004),
|
||||
tregister($02000005),
|
||||
tregister($02000006),
|
||||
tregister($02000007),
|
||||
tregister($02000008),
|
||||
tregister($03000000),
|
||||
tregister($03000001),
|
||||
tregister($03000002),
|
||||
tregister($03000003),
|
||||
tregister($03000004),
|
||||
tregister($03000005),
|
||||
tregister($03000006),
|
||||
tregister($03000007),
|
||||
tregister($04000000),
|
||||
tregister($04000001),
|
||||
tregister($04000002),
|
||||
tregister($04000003),
|
||||
tregister($04000004),
|
||||
tregister($04000005),
|
||||
tregister($04000006),
|
||||
tregister($04000007),
|
||||
tregister($04000008),
|
||||
tregister($04000009),
|
||||
tregister($0400000a),
|
||||
tregister($0400000b),
|
||||
tregister($0400000c),
|
||||
tregister($0400000d),
|
||||
tregister($0400000e),
|
||||
tregister($0400000f)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user