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- removed partial Alpha, IA64 and vis backends since they were never nor

Browse Source 
will likely ever be finished

git-svn-id: trunk@30836 -
This commit is contained in:
Jonas Maebe 2015-05-09 17:25:11 +00:00
parent 1b43930749
commit a04cae2c4b
33 changed files with 2 additions and 6891 deletions
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30
.gitattributes vendored
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@ -53,24 +53,6 @@ compiler/aasmsym.pas svneol=native#text/plain
compiler/aasmtai.pas svneol=native#text/plain
compiler/aggas.pas svneol=native#text/plain
compiler/agjasmin.pas svneol=native#text/plain
compiler/alpha/aasmcpu.pas svneol=native#text/plain
compiler/alpha/agaxpgas.pas svneol=native#text/plain
compiler/alpha/aoptcpu.pas svneol=native#text/plain
compiler/alpha/aoptcpub.pas svneol=native#text/plain
compiler/alpha/aoptcpuc.pas svneol=native#text/plain
compiler/alpha/aoptcpud.pas svneol=native#text/plain
compiler/alpha/cgcpu.pas svneol=native#text/plain
compiler/alpha/cpubase.pas svneol=native#text/plain
compiler/alpha/cpuinfo.pas svneol=native#text/plain
compiler/alpha/cpunode.pas svneol=native#text/plain
compiler/alpha/cpupara.pas svneol=native#text/plain
compiler/alpha/cpupi.pas svneol=native#text/plain
compiler/alpha/cputarg.pas svneol=native#text/plain
compiler/alpha/radirect.pas svneol=native#text/plain
compiler/alpha/rasm.pas svneol=native#text/plain
compiler/alpha/rgcpu.pas svneol=native#text/plain
compiler/alpha/symcpu.pas svneol=native#text/plain
compiler/alpha/tgcpu.pas svneol=native#text/plain
compiler/aopt.pas svneol=native#text/plain
compiler/aoptbase.pas svneol=native#text/plain
compiler/aoptcs.pas svneol=native#text/plain
@ -213,7 +195,6 @@ compiler/i386/cpunode.pas svneol=native#text/plain
compiler/i386/cpupara.pas svneol=native#text/plain
compiler/i386/cpupi.pas svneol=native#text/plain
compiler/i386/cputarg.pas svneol=native#text/plain
compiler/i386/csopt386.pas svneol=native#text/plain
compiler/i386/daopt386.pas svneol=native#text/plain
compiler/i386/hlcgcpu.pas svneol=native#text/plain
compiler/i386/i386att.inc svneol=native#text/plain
@ -250,7 +231,6 @@ compiler/i386/r386std.inc svneol=native#text/plain
compiler/i386/ra386att.pas svneol=native#text/plain
compiler/i386/ra386int.pas svneol=native#text/plain
compiler/i386/rgcpu.pas svneol=native#text/plain
compiler/i386/rropt386.pas svneol=native#text/plain
compiler/i386/symcpu.pas svneol=native#text/plain
compiler/i8086/aoptcpu.pas svneol=native#text/plain
compiler/i8086/aoptcpub.pas svneol=native#text/plain
@ -300,11 +280,6 @@ compiler/i8086/ra8086int.pas svneol=native#text/plain
compiler/i8086/rgcpu.pas svneol=native#text/plain
compiler/i8086/symcpu.pas svneol=native#text/plain
compiler/i8086/tgcpu.pas svneol=native#text/plain
compiler/ia64/aasmcpu.pas svneol=native#text/plain
compiler/ia64/cpubase.pas svneol=native#text/plain
compiler/ia64/cpuinfo.pas svneol=native#text/plain
compiler/ia64/ia64reg.dat svneol=native#text/plain
compiler/ia64/symcpu.pas svneol=native#text/plain
compiler/impdef.pas svneol=native#text/plain
compiler/import.pas svneol=native#text/plain
compiler/jvm/aasmcpu.pas svneol=native#text/plain
@ -815,11 +790,6 @@ compiler/utils/ppuutils/ppuxml.pp svneol=native#text/plain
compiler/utils/samplecfg svneol=native#text/plain
compiler/verbose.pas svneol=native#text/plain
compiler/version.pas svneol=native#text/plain
compiler/vis/aasmcpu.pas svneol=native#text/plain
compiler/vis/cpubase.pas svneol=native#text/plain
compiler/vis/cpuinfo.pas svneol=native#text/plain
compiler/vis/cpunode.pas svneol=native#text/plain
compiler/vis/cpupara.pas svneol=native#text/plain
compiler/widestr.pas svneol=native#text/plain
compiler/wpo.pas svneol=native#text/plain
compiler/wpobase.pas svneol=native#text/plain

11
compiler/Makefile
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@ -330,9 +330,6 @@ override PACKAGE_VERSION=3.1.1
unexport FPC_VERSION FPC_COMPILERINFO
CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64
ALLTARGETS=$(CYCLETARGETS)
ifdef ALPHA
PPC_TARGET=alpha
endif
ifdef POWERPC
PPC_TARGET=powerpc
endif
@ -436,9 +433,6 @@ MSGFILES=$(wildcard msg/error*.msg)
ifeq ($(CPC_TARGET),i386)
CPUSUF=386
endif
ifeq ($(CPC_TARGET),alpha)
CPUSUF=axp
endif
ifeq ($(CPC_TARGET),m68k)
CPUSUF=68k
endif
@ -3861,7 +3855,7 @@ INSTALLEXEFILE=$(PPCROSSNAME)
else
INSTALLEXEFILE=$(EXENAME)
endif
PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 alpha vis ia64 mips mipsel avr jvm i8086 aarch64
PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64
INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
.PHONY: $(PPC_TARGETS) $(INSTALL_TARGETS)
$(PPC_TARGETS):
@ -3936,9 +3930,6 @@ insdat: insdatx86 insdatarm insdataarch64
regdatarm : arm/armreg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkarmreg.pp
cd arm && ..$(PATHSEP)utils$(PATHSEP)mkarmreg$(SRCEXEEXT)
regdatia64 : ia64/ia64reg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkia64reg.pp
cd ia64 && ..$(PATHSEP)utils$(PATHSEP)mkia64reg$(SRCEXEEXT)
regdatsp : sparc/spreg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkspreg.pp
cd sparc && ..$(PATHSEP)utils$(PATHSEP)mkspreg$(SRCEXEEXT)

12
compiler/Makefile.fpc
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@ -38,9 +38,6 @@ CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr
ALLTARGETS=$(CYCLETARGETS)
# Allow ALPHA, POWERPC, POWERPC64, M68K, I386, jvm defines for target cpu
ifdef ALPHA
PPC_TARGET=alpha
endif
ifdef POWERPC
PPC_TARGET=powerpc
endif
@ -172,9 +169,6 @@ MSGFILES=$(wildcard msg/error*.msg)
ifeq ($(CPC_TARGET),i386)
CPUSUF=386
endif
ifeq ($(CPC_TARGET),alpha)
CPUSUF=axp
endif
ifeq ($(CPC_TARGET),m68k)
CPUSUF=68k
endif
@ -406,7 +400,7 @@ endif
# CPU targets
#####################################################################
PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 alpha vis ia64 mips mipsel avr jvm i8086 aarch64
PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64
INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
.PHONY: $(PPC_TARGETS) $(INSTALL_TARGETS)
@ -521,10 +515,6 @@ regdatarm : arm/armreg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkarmreg.pp
cd arm && ..$(PATHSEP)utils$(PATHSEP)mkarmreg$(SRCEXEEXT)
regdatia64 : ia64/ia64reg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkia64reg.pp
cd ia64 && ..$(PATHSEP)utils$(PATHSEP)mkia64reg$(SRCEXEEXT)
regdatsp : sparc/spreg.dat
$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkspreg.pp
cd sparc && ..$(PATHSEP)utils$(PATHSEP)mkspreg$(SRCEXEEXT)

268
compiler/alpha/aasmcpu.pas
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@ -1,268 +0,0 @@
{
Copyright (c) 1998-2000 by Florian Klaempfl
Implements the assembler classes specific for the Alpha
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
Implements the assembler classes specific for the Alpha.
}
unit aasmcpu;
{$i fpcdefs.inc}
interface
uses
aasmbase,globals,verbose,
cpubase,aasmtai,aasmdata,aasmsym;
type
tai_frame = class(tai)
G,R : TRegister;
LS,LU : longint;
Constructor Create (GP : Tregister; Localsize : Longint; RA : TRegister; L : longint);
end;
taicpu = class(tai_cpu_abstract_sym)
constructor op_none(op : tasmop);
constructor op_reg(op : tasmop;_op1 : tregister);
constructor op_const(op : tasmop;_op1 : longint);
constructor op_ref(op : tasmop;_op1 : preference);
constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
constructor op_reg_ref(op : tasmop;_op1 : tregister;_op2 : preference);
constructor op_reg_const(op:tasmop; _op1: tregister; _op2: longint);
constructor op_const_reg(op : tasmop;_op1 : longint;_op2 : tregister);
constructor op_const_const(op : tasmop;_op1,_op2 : longint);
constructor op_const_ref(op : tasmop;_op1 : longint;_op2 : preference);
constructor op_ref_reg(op : tasmop;_op1 : preference;_op2 : tregister);
{ this is only allowed if _op1 is an int value (_op1^.isintvalue=true) }
constructor op_ref_ref(op : tasmop;_op1,_op2 : preference);
constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
constructor op_reg_const_reg(op : tasmop;_op1 : tregister;_op2 : longint;_op3 : tregister);
constructor op_const_ref_reg(op : tasmop;_op1 : longint;_op2 : preference;_op3 : tregister);
constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; _op3 : preference);
constructor op_const_reg_ref(op : tasmop;_op1 : longint;_op2 : tregister;_op3 : preference);
constructor op_reg_ref_const(op : tasmop;_op1 : tregister;_op2 : preference;_op3 : longint);
{ this is for Jmp instructions }
constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
constructor op_sym(op : tasmop;_op1 : tasmsymbol);
constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
constructor op_sym_ofs_reg(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;_op2 : preference);
end;
tai_align = class(tai_align_abstract)
{ nothing to add }
end;
procedure InitAsm;
procedure DoneAsm;
implementation
{*****************************************************************************
taicpu Constructors
*****************************************************************************}
constructor taicpu.op_none(op : tasmop);
begin
inherited create(op);
end;
constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
begin
inherited create(op);
ops:=1;
end;
constructor taicpu.op_const(op : tasmop;_op1 : longint);
begin
inherited create(op);
ops:=1;
end;
constructor taicpu.op_ref(op : tasmop;_op1 : preference);
begin
inherited create(op);
ops:=1;
end;
constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: longint);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;_op2 : preference);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_const_reg(op : tasmop;_op1 : longint;_op2 : tregister);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_const_const(op : tasmop;_op1,_op2 : longint);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_const_ref(op : tasmop;_op1 : longint;_op2 : preference);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_ref_reg(op : tasmop;_op1 : preference;_op2 : tregister);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_ref_ref(op : tasmop;_op1,_op2 : preference);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_reg_const_reg(op : tasmop;_op1 : tregister;_op2 : longint;_op3 : tregister);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister;_op3 : preference);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_const_ref_reg(op : tasmop;_op1 : longint;_op2 : preference;_op3 : tregister);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_const_reg_ref(op : tasmop;_op1 : longint;_op2 : tregister;_op3 : preference);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_reg_ref_const(op : tasmop;_op1 : tregister;_op2 : preference;_op3 : longint);
begin
inherited create(op);
ops:=3;
end;
constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
begin
inherited create(op);
condition:=cond;
ops:=1;
end;
constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
begin
inherited create(op);
ops:=1;
end;
constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
begin
inherited create(op);
ops:=1;
end;
constructor taicpu.op_sym_ofs_reg(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
begin
inherited create(op);
ops:=2;
end;
constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;_op2 : preference);
begin
inherited create(op);
ops:=2;
end;
Constructor tai_frame.create (GP : Tregister; Localsize : Longint; RA : TRegister; L : longint);
begin
Inherited Create;
typ:=ait_frame;
G:=GP;
R:=RA;
LS:=LocalSize;
LU:=L;
end;
procedure InitAsm;
begin
end;
procedure DoneAsm;
begin
end;
end.

126
compiler/alpha/agaxpgas.pas
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@ -1,126 +0,0 @@
{
Copyright (c) 1998-2000 by Florian Klaempfl
This unit implements an asm for the DEC Alpha
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit agaxpgas;
{$i fpcdefs.inc}
interface
uses
globals,systems,aasmbase,aasmtai,aasmdata,
aggas,cpubase;
type
TAXPGNUAssembler=class(TGNUAssembler)
procedure WriteInstruction(hp : tai);override;
end;
const
gas_reg2str : array[tregister] of string[4] = (
'',
'','','','','','','','','','',
'','','','','','','','','','',
'','','','','','','','','','',
'','',
'','','','','','','','','','',
'','','','','','','','','','',
'','','','','','','','','','',
'',''
);
implementation
const
op2str : array[tasmop] of string[14] = (
'addf','addg','addl','addq',
'adds','addt','amask','and','beq','bge',
'bgt','bic','bis','blbc','blbs','ble',
'blt','bne','br','bsr','call_pal','cmoveq',
'cmovge','cmovgt','cmovlbc','cmovlbs','cmovle','cmovlt',
'cmovne','cmpbge','cmpeq','cmpgeq','cmpgle','cmpglt',
'cmple','cmplt','cmpteq','cmptle','cmptlt','cmptun',
'cmpule','cmpult','cpys','cpyse','cpysn','ctlz',
'ctpop','cttz','cvtdg','cvtgd','cvtgf','cvtgq',
'cvtlq','cvtqf','cvtqg','cvtql','cvtqs','cvtqt',
'cvtst','cvttq','cvtts','divf','divg','divs',
'divt','ecb','eqv','excb','extbl','extlh',
'extll','extqh','extql','extwh','extwl','fbeq',
'fbge','fbgt','fble','fblt','fbne','fcmoveq',
'fcmovge','fcmovgt','fcmovle','fcmovlt','fcmovne','fetch',
'fetch_m','ftois','ftoit','implver','insbl','inslh',
'insll','insqh','insql','inswh','inswl','itoff',
'itofs','itoft','jmp','jsr','jsr_coroutine','lda',
'ldah','ldbu','ldwu','ldf','ldg','ldl',
'ldl_l','ldq','ldq_l','ldq_u','lds','ldt',
'maxsb8','maxsw4','maxub8','maxuw4','mb','mf_fpcr',
'minsb8','minsw4','minub8','minuw4','mskbl','msklh',
'mskll','mskqh','mskql','mskwh','mskwl','mt_fpcr',
'mulf','mulg','mull','mulq',
'muls','mult','ornot','perr','pklb','pkwb',
'rc','ret','rpcc','rs','s4addl','s4addq',
's4subl','s4subq','s8addl','s8addq','s8subl','s8subq',
'sextb','sextw','sll','sqrtf','sqrtg','sqrts',
'sqrtt','sra','srl','stb','stf','stg',
'sts','stl','stl_c','stq','stq_c','stq_u',
'stt','stw','subf','subg','subl',
'subq','subs','subt','trapb','umulh','unpkbl',
'unpkbw','wh64','wmb','xor','zap','zapnot',
'ldgp');
procedure TAXPGNUAssembler.WriteInstruction (hp : tai);
begin
(*
op:=paicpu(hp)^.opcode;
calljmp:=is_calljmp(op);
{ call maybe not translated to calll }
s:=#9+att_op2str[op]+cond2str[paicpu(hp)^.condition];
if (not calljmp) and
(not att_nosuffix[op]) and
not(
(paicpu(hp)^.oper[0].typ=top_reg) and
(paicpu(hp)^.oper[0].reg in [R_ST..R_ST7])
) then
s:=s+att_opsize2str[paicpu(hp)^.opsize];
{ process operands }
if paicpu(hp)^.ops<>0 then
begin
{ call and jmp need an extra handling }
{ this code is only called if jmp isn't a labeled instruction }
if calljmp then
s:=s+#9+getopstr_jmp(paicpu(hp)^.oper[0])
else
begin
for i:=0to paicpu(hp)^.ops-1 do
begin
if i=0 then
sep:=#9
else
sep:=',';
s:=s+sep+getopstr(paicpu(hp)^.oper[i])
end;
end;
end;
AsmWriteLn(s);
*)
end;
end.

38
compiler/alpha/aoptcpu.pas
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@ -1,38 +0,0 @@
{
Copyright (c) 1998-2000 by Jonas Maebe, member of the Free Pascal
Development Team
This unit implements the Alpha optimizer object
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
Unit aoptcpu;
Interface
uses cpubase, aoptobj, aoptcpub;
Type
TAOptCpu = Object(TAoptObj)
{ uses the same constructor as TAopObj }
End;
Implementation
End.

112
compiler/alpha/aoptcpub.pas
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@ -1,112 +0,0 @@
{
Copyright (c) 1998-2000 by Jonas Maebe, member of the Free Pascal
Development Team
This unit contains several types and constants necessary for the
optimizer to work on the 80x86 architecture
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
Unit aoptcpub; { Assembler OPTimizer CPU specific Base }
{ enable the following define if memory references can have both a base and }
{ index register in 1 operand }
{ enable the following define if memory references can have a scaled index }
{$define RefsHaveScale}
{ enable the following define if memory references can have a segment }
{ override }
{ define RefsHaveSegment}
Interface
Uses
CPUAsm,AOptBase;
Type
{ type of a normal instruction }
TInstr = Taicpu;
PInstr = ^TInstr;
{ ************************************************************************* }
{ **************************** TCondRegs ********************************** }
{ ************************************************************************* }
{ Info about the conditional registers }
TCondRegs = Object
Constructor Init;
Destructor Done;
End;
{ ************************************************************************* }
{ **************************** TAoptBaseCpu ******************************* }
{ ************************************************************************* }
TAoptBaseCpu = Object(TAoptBase)
End;
{ ************************************************************************* }
{ ******************************* Constants ******************************* }
{ ************************************************************************* }
Const
{ the maximum number of things (registers, memory, ...) a single instruction }
{ changes }
MaxCh = 3;
{ the maximum number of operands an instruction has }
MaxOps = 3;
{Oper index of operand that contains the source (reference) with a load }
{instruction }
LoadSrc = 0;
{Oper index of operand that contains the destination (register) with a load }
{instruction }
LoadDst = 1;
{Oper index of operand that contains the source (register) with a store }
{instruction }
StoreSrc = 0;
{Oper index of operand that contains the destination (reference) with a load }
{instruction }
StoreDst = 1;
Implementation
{ ************************************************************************* }
{ **************************** TCondRegs ********************************** }
{ ************************************************************************* }
Constructor TCondRegs.init;
Begin
End;
Destructor TCondRegs.Done; {$ifdef inl} inline; {$endif inl}
Begin
End;
End.

38
compiler/alpha/aoptcpuc.pas
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@ -1,38 +0,0 @@
{
Copyright (c) 1998-2000 by Jonas Maebe, member of the Free Pascal
Development Team
This unit contains the processor specific implementation of the
assembler optimizer common subexpression elimination object.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit aoptcpuc;
Interface
Uses
AOptCs;
Type
TRegInfoCpu = Object(TRegInfo)
End;
Implementation
End.

39
compiler/alpha/aoptcpud.pas
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@ -1,39 +0,0 @@
{
Copyright (c) 1998-2000 by Jonas Maebe, member of the Free Pascal
Development Team
This unit contains the processor specific implementation of the
assembler optimizer data flow analyzer.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
Unit aoptcpud;
Interface
uses
AOptDA;
Type
PAOptDFACpu = ^TAOptDFACpu;
TAOptDFACpu = Object(TAOptDFA)
End;
Implementation
End.

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compiler/alpha/cgcpu.pas
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{
Copyright (c) 1998-2000 by Florian Klaempfl
This unit implements the code generator for the Alpha
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit implements the code generator for the Alpha.
}
unit cgcpu;
{$i fpcdefs.inc}
interface
uses
cgbase,cgobj,aasmbase,aasmtai,aasmdata,aasmcpu,cginfo,cpubase,cpuinfo;
type
pcgalpha = ^tcgalpha;
tcgalpha = class(tcg)
procedure a_call_name(list : TAsmList;const s : string);override;
procedure a_load_const_reg(list : TAsmList;size : tcgsize;a : aword;register : tregister);override;
procedure a_load_reg_ref(list : TAsmList;size : tcgsize;register : tregister;const ref : treference);override;
procedure a_load_ref_reg(list : TAsmList;size : tcgsize;const ref : treference;register : tregister);override;
procedure a_load_reg_reg(list : TAsmList;fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aword;
reg : tregister; l : tasmlabel);override;
procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
procedure a_cmp_reg_ref_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg : tregister;l : tasmlabel);
procedure a_cmp_ref_const_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aword;
reg : tregister; l : tasmlabel);
procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
procedure g_stackframe_entry(list : TAsmList;localsize : longint);override;
procedure g_maybe_loadself(list : TAsmList);override;
procedure g_restore_frame_pointer(list : TAsmList);override;
end;
procedure create_codegen;
implementation
uses
globtype,globals;
procedure tcgalpha.g_stackframe_entry(list : TAsmList;localsize : longint);
begin
list.concat(taicpu.op_reg_ref(A_LDGP,Global_pointer,new_reference(R_27,0)));
list.concat(taicpu.op_reg_ref(A_LDA,stack_pointer_reg,new_reference(stack_pointer_reg,-LocalSize)));
If LocalSize<>0 then
list.concat(tai_frame.create(Global_pointer,LocalSize,R_27,0));
{ Always generate a frame pointer. }
list.concat(taicpu.op_reg_reg_reg(A_BIS,stack_pointer_reg,stack_pointer_reg,frame_pointer_reg));
end;
procedure g_exitcode(list : TAsmList;parasize : longint; nostackframe,inlined : boolean);
begin
{ Restore stack pointer from frame pointer }
list.Concat (taicpu.op_reg_reg_reg(A_BIS,frame_pointer_reg,frame_pointer_reg,stack_pointer_reg));
{ Restore previous stack position}
list.Concat (taicpu.op_reg_const_reg(A_ADDQ,stack_pointer_reg,Parasize,stack_pointer_reg));
{ return... }
list.Concat(taicpu.op_reg_ref_const(A_RET,stack_pointer_reg,new_reference(Return_pointer,0),1));
{ end directive
Concat (paiend,init(''));
}
end;
procedure tcgalpha.a_call_name(list : TAsmList;const s : string);
begin
{ list^.concat(taicpu,op_sym(A_CALL,S_NO,newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION)))); }
{!!!!!!!!!1 offset is ignored }
abstract;
end;
procedure tcgalpha.a_load_const_reg(list : TAsmList;size : tcgsize;a : aword;register : tregister);
begin
end;
procedure tcgalpha.a_load_reg_ref(list : TAsmList;size : tcgsize;register : tregister;const ref : treference);
begin
end;
procedure tcgalpha.a_load_ref_reg(list : TAsmList;size : tcgsize;const ref : treference;register : tregister);
begin
end;
procedure tcgalpha.a_load_reg_reg(list : TAsmList;fromsize, tosize : tcgsize;reg1,reg2 : tregister);
begin
end;
procedure tcgalpha.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aword;reg : tregister;
l : tasmlabel);
begin
end;
procedure tcgalpha.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
begin
end;
procedure tcgalpha.a_cmp_reg_ref_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg : tregister;l : tasmlabel);
begin
end;
procedure tcgalpha.a_cmp_ref_const_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aword;
reg : tregister; l : tasmlabel);
begin
end;
procedure tcgalpha.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
begin
end;
procedure tcgalpha.g_maybe_loadself(list : TAsmList);
begin
end;
procedure tcgalpha.g_restore_frame_pointer(list : TAsmList);
begin
end;
procedure create_codegen;
begin
cg:=tcgalpha.create;
cg128:=tcg128.create;
end;
end.

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compiler/alpha/cpubase.pas
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@ -1,431 +0,0 @@
{
Copyright (C) 1998-2000 by Florian Klaempfl
This unit implements an asmlistitem class for the Alpha architecture.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit implements an asmlistitem class for the Alpha architecture.
}
unit cpubase;
{$i fpcdefs.inc}
interface
uses
cutils,cclasses,globals,aasmbase,cpuinfo,cginfo;
type
{ all registers }
TRegister = (R_NO, { R_NO is Mandatory, signifies no register }
R_0,R_1,R_2,R_3,R_4,R_5,R_6,R_7,R_8,R_9,
R_10,R_11,R_12,R_13,R_14,R_15,R_16,R_17,R_18,R_19,
R_20,R_21,R_22,R_23,R_24,R_25,R_26,R_27,R_28,R_29,
R_30,R_31,
R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,
R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,
R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
R_F30,R_F31);
tasmop = (A_ADDF,A_ADDG,A_ADDL,A_ADDQ,
A_ADDS,A_ADDT,A_AMASK,A_AND,A_BEQ,A_BGE,
A_BGT,A_BIC,A_BIS,A_BLBC,A_BLBS,A_BLE,
A_BLT,A_BNE,A_BR,A_BSR,A_CALL_PAL,A_CMOVEQ,
A_CMOVGE,A_CMOVGT,A_CMOVLBC,A_CMOVLBS,A_CMOVLE,A_CMOVLT,
A_CMOVNE,A_CMPBGE,A_CMPEQ,A_CMPGEQ,A_CMPGLE,A_CMPGLT,
A_CMPLE,A_CMPLT,A_CMPTEQ,A_CMPTLE,A_CMPTLT,A_CMPTUN,
A_CMPULE,A_CMPULT,A_CPYS,A_CPYSE,A_CPYSN,A_CTLZ,
A_CTPOP,A_CTTZ,A_CVTDG,A_CVTGD,A_CVTGF,A_CVTGQ,
A_CVTLQ,A_CVTQF,A_CVTQG,A_CVTQL,A_CVTQS,A_CVTQT,
A_CVTST,A_CVTTQ,A_CVTTS,A_DIVF,A_DIVG,A_DIVS,
A_DIVT,A_ECB,A_EQV,A_EXCB,A_EXTBL,A_EXTLH,
A_EXTLL,A_EXTQH,A_EXTQL,A_EXTWH,A_EXTWL,A_FBEQ,
A_FBGE,A_FBGT,A_FBLE,A_FBLT,A_FBNE,A_FCMOVEQ,
A_FCMOVGE,A_FCMOVGT,A_FCMOVLE,A_FCMOVLT,A_FCMOVNE,A_FETCH,
A_FETCH_M,A_FTOIS,A_FTOIT,A_IMPLVER,A_INSBL,A_INSLH,
A_INSLL,A_INSQH,A_INSQL,A_INSWH,A_INSWL,A_ITOFF,
A_ITOFS,A_ITOFT,A_JMP,A_JSR,A_JSR_COROUTINE,A_LDA,
A_LDAH,A_LDBU,A_LDWU,A_LDF,A_LDG,A_LDL,
A_LDL_L,A_LDQ,A_LDQ_L,A_LDQ_U,A_LDS,A_LDT,
A_MAXSB8,A_MAXSW4,A_MAXUB8,A_MAXUW4,A_MB,A_MF_FPCR,
A_MINSB8,A_MINSW4,A_MINUB8,A_MINUW4,A_MSKBL,A_MSKLH,
A_MSKLL,A_MSKQH,A_MSKQL,A_MSKWH,A_MSKWL,A_MT_FPCR,
A_MULF,A_MULG,A_MULL,A_MULQ,
A_MULS,A_MULT,A_ORNOT,A_PERR,A_PKLB,A_PKWB,
A_RC,A_RET,A_RPCC,A_RS,A_S4ADDL,A_S4ADDQ,
A_S4SUBL,A_S4SUBQ,A_S8ADDL,A_S8ADDQ,A_S8SUBL,A_S8SUBQ,
A_SEXTB,A_SEXTW,A_SLL,A_SQRTF,A_SQRTG,A_SQRTS,
A_SQRTT,A_SRA,A_SRL,A_STB,A_STF,A_STG,
A_STS,A_STL,A_STL_C,A_STQ,A_STQ_C,A_STQ_U,
A_STT,A_STW,A_SUBF,A_SUBG,A_SUBL,
A_SUBQ,A_SUBS,A_SUBT,A_TRAPB,A_UMULH,
A_UNPKBL,A_UNPKBW,A_WH64,A_WMB,A_XOR,A_ZAP,
A_ZAPNOT
{ Psuedo code understood by the gnu assembler }
,A_LDGP);
const
firstop = low(tasmop);
lastop = high(tasmop);
std_reg2str : array[tregister] of string[4] = (
'',
'','','','','','','','','','',
'','','','','','','','','','',
'','','','','','','','','','',
'','',
'','','','','','','','','','',
'','','','','','','','','','',
'','','','','','','','','','',
'',''
);
type
TAsmCond =
(
C_None,C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,C_NS,C_NZ,C_O,C_P,
C_PE,C_PO,C_S,C_Z
);
TRegisterset = Set of TRegister;
tregister64 = tregister;
Const
Firstreg = R_0;
LastReg = R_F31;
{*****************************************************************************
Default generic sizes
*****************************************************************************}
{ Defines the default address size for a processor, }
OS_ADDR = OS_64;
{ the natural int size for a processor,
has to match osuinttype/ossinttype as initialized in psystem }
OS_INT = OS_64;
{ the maximum float size for a processor, }
OS_FLOAT = OS_F80;
{ the size of a vector register for a processor }
OS_VECTOR = OS_M64;
stack_pointer_reg = R_30;
frame_pointer_reg = R_15;
self_pointer_reg = R_16;
accumulator = R_0;
{the return_result_reg, is used inside the called function to store its return
value when that is a scalar value otherwise a pointer to the address of the
result is placed inside it}
return_result_reg = accumulator;
{the function_result_reg contains the function result after a call to a scalar
function othewise it contains a pointer to the returned result}
function_result_reg = accumulator;
fpu_result_reg = R_F0;
global_pointer = R_29;
return_pointer = R_26;
{ it is used to pass the offset to the destructor helper routine }
vmt_offset_reg = R_1;
{ low and high of the available maximum width integer general purpose }
{ registers }
LoGPReg = R_0;
HiGPReg = R_31;
{ low and high of every possible width general purpose register (same as
above on most architctures apart from the 80x86) }
LoReg = R_0;
HiReg = R_31;
maxfpuregs = 32;
max_operands = 4;
registers_saved_on_cdecl = [R_9..R_14,R_F2..R_F9];
maxvarregs = 6;
varregs : Array [1..maxvarregs] of Tregister =
(R_9,R_10,R_11,R_12,R_13,R_14);
maxfpuvarregs = 8;
{ Registers which are defined as scratch and no need to save across
routine calls or in assembler blocks.
}
max_scratch_regs = 2;
scratch_regs : array[1..max_scratch_regs] of tregister = (R_1,R_2);
{*****************************************************************************
GDB Information
*****************************************************************************}
{ Register indexes for stabs information, when some
parameters or variables are stored in registers.
}
stab_regindex : array[tregister] of shortint =
(0,
0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,
0,0,
0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,
0,0
);
{*****************************************************************************
Flags
*****************************************************************************}
type
{ The Alpha doesn't have flags but some generic code depends on this type. }
TResFlags = (F_NO);
{ reference record }
pparareference = ^tparareference;
tparareference = packed record
index : tregister;
offset : longint;
end;
trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
TReference = record
offset : aword;
symbol : tasmsymbol;
base : tregister;
{ The index isn't used by the alpha port, but some generic code depends on it }
index : tregister;
is_immediate : boolean;
offsetfixup : word; {needed for inline}
options : trefoptions;
{ the boundary to which the reference is surely aligned }
alignment : byte;
end;
PReference = ^TReference;
TLoc=(
LOC_INVALID, { added for tracking problems}
LOC_CONSTANT, { constant value }
LOC_JUMP, { boolean results only, jump to false or true label }
LOC_FLAGS, { boolean results only, flags are set }
LOC_CREFERENCE, { in memory constant value reference (cannot change) }
LOC_REFERENCE, { in memory value }
LOC_REGISTER, { in a processor register }
LOC_CREGISTER, { Constant register which shouldn't be modified }
LOC_FPUREGISTER, { FPU stack }
LOC_CFPUREGISTER, { if it is a FPU register variable on the fpu stack }
LOC_SSEREGISTER,
LOC_CSSEREGISTER,
LOC_CMMREGISTER,
LOC_MMREGISTER
);
{ tparamlocation describes where a parameter for a procedure is stored.
References are given from the caller's point of view. The usual
TLocation isn't used, because contains a lot of unnessary fields.
}
tparalocation = packed record
size : TCGSize;
loc : TLoc;
sp_fixup : longint;
case TLoc of
LOC_REFERENCE : (reference : tparareference);
{ segment in reference at the same place as in loc_register }
LOC_REGISTER,LOC_CREGISTER : (
case longint of
1 : (register,register64.reghi : tregister);
{ overlay a register64.reglo }
2 : (register64.reglo : tregister);
{ overlay a 64 Bit register type }
3 : (reg64 : tregister64);
4 : (register64 : tregister64);
);
end;
tlocation = packed record
loc : TLoc;
size : TCGSize;
case TLoc of
LOC_CONSTANT : (
case longint of
1 : (value : AWord);
{ can't do this, this layout depends on the host cpu. Use }
{ lo(valueqword)/hi(valueqword) instead (JM) }
{ 2 : (valuelow, valuehigh:AWord); }
{ overlay a complete 64 Bit value }
3 : (valueqword : qword);
);
LOC_CREFERENCE,
LOC_REFERENCE : (reference : treference);
{ segment in reference at the same place as in loc_register }
LOC_REGISTER,LOC_CREGISTER : (
case longint of
1 : (register,register64.reghi,segment : tregister);
{ overlay a register64.reglo }
2 : (register64.reglo : tregister);
{ overlay a 64 Bit register type }
3 : (reg64 : tregister64);
4 : (register64 : tregister64);
);
end;
{*****************************************************************************
Operands
*****************************************************************************}
{ Types of operand }
toptype=(top_none,top_reg,top_ref,top_const,top_symbol);
toper=record
ot : longint;
case typ : toptype of
top_none : ();
top_reg : (reg:tregister);
top_ref : (ref:preference);
top_const : (val:longint);
top_symbol : (sym:tasmsymbol;symofs:longint);
end;
const
{ Registers which must be saved when calling a routine declared as
cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
saved should be the ones as defined in the target ABI and / or GCC.
This value can be deduced from the CALLED_USED_REGISTERS array in the
GCC source.
}
std_saved_registers = [];
{ Required parameter alignment when calling a routine declared as
stdcall and cdecl. The alignment value should be the one defined
by GCC or the target ABI.
The value of this constant is equal to the constant
PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
}
std_param_align = 8;
{ offsets for the integer and floating point registers }
INT_REG = 0;
FLOAT_REG = 32;
{ operator qualifiers }
OQ_CHOPPED_ROUNDING = $01; { /C }
OQ_ROUNDING_MODE_DYNAMIC = $02; { /D }
OQ_ROUND_TOWARD_MINUS_INFINITY = $04; { /M }
OQ_INEXACT_RESULT_ENABLE = $08; { /I }
OQ_SOFTWARE_COMPLETION_ENABLE = $10; { /S }
OQ_FLOATING_UNDERFLOW_ENABLE = $20; { /U }
OQ_INTEGER_OVERFLOW_ENABLE = $40; { /V }
{*****************************************************************************
Opcode propeties (needed for optimizer)
*****************************************************************************}
{$ifndef NOOPT}
Type
{What an instruction can change}
TInsChange = (Ch_None);
{$endif}
{ resets all values of ref to defaults }
procedure reset_reference(var ref : treference);
{ set mostly used values of a new reference }
function new_reference(base : tregister;offset : longint) : preference;
function newreference(const r : treference) : preference;
procedure disposereference(var r : preference);
function reg2str(r : tregister) : string;
{*****************************************************************************
Init/Done
*****************************************************************************}
procedure InitCpu;
procedure DoneCpu;
implementation
uses
verbose;
function reg2str(r : tregister) : string;
begin
if r in [R_0..R_31] then
reg2str:='R'+tostr(longint(r)-longint(R_0))
else if r in [R_F0..R_F31] then
reg2str:='F'+tostr(longint(r)-longint(R_F0))
else internalerror(38991);
end;
procedure reset_reference(var ref : treference);
begin
FillChar(ref,sizeof(treference),0);
end;
function new_reference(base : tregister;offset : longint) : preference;
var
r : preference;
begin
new(r);
FillChar(r^,sizeof(treference),0);
r^.offset:=offset;
r^.alignment:=8;
new_reference:=r;
end;
function newreference(const r : treference) : preference;
var
p : preference;
begin
new(p);
p^:=r;
newreference:=p;
end;
procedure disposereference(var r : preference);
begin
dispose(r);
r:=Nil;
end;
{*****************************************************************************
Init/Done
*****************************************************************************}
procedure InitCpu;
begin
end;
procedure DoneCpu;
begin
end;
end.

91
compiler/alpha/cpuinfo.pas
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@ -1,91 +0,0 @@
{
This file is part of the Free Pascal run time library.
Copyright (c) 1998-2000 by the Free Pascal development team
Basic Processor information about the Alpha
See the file COPYING.FPC, included in this distribution,
for details about the copyright.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
**********************************************************************}
{
Basic Processor information about the Alpha
}
Unit CPUInfo;
{$i fpcdefs.inc}
Interface
uses
globtype;
Type
{ Natural integer register type and size for the target machine }
{$ifdef FPC}
AWord = Qword;
{$else FPC}
AWord = Longint;
{$endif FPC}
PAWord = ^AWord;
{ This must be an ordinal type with the same size as a pointer
Note: Must be unsigned! Otherwise, ugly code like
pointer(-1) will result in a pointer with the value
$fffffffffffffff on a 32bit machine if the compiler uses
int64 constants internally (JM) }
TConstPtrUInt = qword;
bestreal = extended;
{$if FPC_FULLVERSION>20700}
bestrealrec = TExtended80Rec;
{$endif FPC_FULLVERSION>20700}
ts32real = single;
ts64real = double;
ts80real = extended;
ts64comp = extended;
pbestreal=^bestreal;
{ possible supported processors for this target }
tcputype =
(cpu_none,
ClassEV7,
ClassEV8
);
tcontrollertype =
(ct_none
);
Const
{ Is there support for dealing with multiple microcontrollers available }
{ for this platform? }
ControllerSupport = false;
{ Size of native extended type }
extended_size = 16;
{# Size of a pointer }
aint_size = 8;
{# Size of a multimedia register }
mmreg_size = 8;
{ We know that there are fields after sramsize
but we don't care about this warning }
{$PUSH}
{$WARN 3177 OFF}
embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
(
(controllertypestr:''; controllerunitstr:''; flashbase:0; flashsize:0; srambase:0; sramsize:0));
{$POP}
{ target cpu string (used by compiler options) }
target_cpu_string = 'alpha';
Implementation
end.

56
compiler/alpha/cpunode.pas
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@ -1,56 +0,0 @@
{
Copyright (c) 2000-2002 by Florian Klaempfl
Imports the Alpha code generator
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit imports the Alpha code generator.
}
unit cpunode;
{$i fpcdefs.inc}
interface
implementation
uses
{ generic nodes }
ncgbas,ncgld,ncgflw,ncgcnv,ncgmem,ncgcon,ncgcal,ncgset,ncginl,
{ to be able to only parts of the generic code,
the processor specific nodes must be included
after the generic one (FK)
}
// naxpadd,
// naxpcal,
// naxpcon,
// naxpflw,
// naxpmem,
// naxpset,
// naxpinl,
// nppcopt,
{ this not really a node }
// naxpobj,
// naxpmat,
// naxpcnv,
{ symtable }
symcpu
;
end.

270
compiler/alpha/cpupara.pas
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@ -1,270 +0,0 @@
{
Copyright (c) 2002 by Florian Klaempfl
Alpha specific calling conventions
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{ Alpha specific calling conventions are handled by this unit
}
unit cpupara;
{$i fpcdefs.inc}
interface
uses
cpubase,
symconst,symbase,symtype,symdef,paramgr;
type
tcpuparamanager = class(tparamanager)
procedure create_param_loc_info(p : tabstractprocdef);override;
function getfuncretparaloc(p : tabstractprocdef) : tparalocation;override;
end;
implementation
uses
verbose,
globtype,
cpuinfo,cginfo,cgbase,
defbase;
function getparaloc(p : tdef) : tloc;
begin
{ Later, the LOC_REFERENCE is in most cases changed into LOC_REGISTER
if push_addr_param for the def is true
}
case p.typ of
orddef:
getparaloc:=LOC_REGISTER;
floatdef:
getparaloc:=LOC_FPUREGISTER;
enumdef:
getparaloc:=LOC_REGISTER;
pointerdef:
getparaloc:=LOC_REGISTER;
formaldef:
getparaloc:=LOC_REGISTER;
classrefdef:
getparaloc:=LOC_REGISTER;
recorddef:
getparaloc:=LOC_REFERENCE;
objectdef:
if is_object(p) then
getparaloc:=LOC_REFERENCE
else
getparaloc:=LOC_REGISTER;
stringdef:
if is_shortstring(p) or is_longstring(p) then
getparaloc:=LOC_REFERENCE
else
getparaloc:=LOC_REGISTER;
procvardef:
if (po_methodpointer in tprocvardef(p).procoptions) then
getparaloc:=LOC_REFERENCE
else
getparaloc:=LOC_REGISTER;
filedef:
getparaloc:=LOC_REGISTER;
arraydef:
getparaloc:=LOC_REFERENCE;
setdef:
if is_smallset(p) then
getparaloc:=LOC_REGISTER
else
getparaloc:=LOC_REFERENCE;
variantdef:
getparaloc:=LOC_REFERENCE;
{ avoid problems with errornous definitions }
errordef:
getparaloc:=LOC_REGISTER;
else
internalerror(2002071001);
end;
end;
procedure tcpuparamanager.create_param_loc_info(p : tabstractprocdef);
var
nextintreg,nextfloatreg,nextmmreg : tregister;
stack_offset : aword;
hp : tparaitem;
loc : tloc;
is_64bit: boolean;
begin
nextintreg:=R_3;
nextfloatreg:=R_F1;
// nextmmreg:=R_M1;
stack_offset:=0;
{ pointer for structured results ? }
if not is_void(p.returndef) then
begin
if not(ret_in_reg(p.returndef)) then
inc(nextintreg);
end;
{ frame pointer for nested procedures? }
{ inc(nextintreg); }
{ constructor? }
{ destructor? }
hp:=tparaitem(p.para.last);
while assigned(hp) do
begin
loc:=getparaloc(hp.paratype.def);
hp.paraloc.sp_fixup:=0;
case loc of
LOC_REGISTER:
begin
hp.paraloc.size := def_cgsize(hp.paratype.def);
{ for things like formaldef }
if hp.paraloc.size = OS_NO then
hp.paraloc.size := OS_ADDR;
is_64bit := hp.paraloc.size in [OS_64,OS_S64];
if nextintreg<=tregister(ord(R_10)-ord(is_64bit)) then
begin
hp.paraloc.loc:=LOC_REGISTER;
hp.paraloc.register64.reglo:=nextintreg;
inc(nextintreg);
if is_64bit then
begin
hp.paraloc.register64.reghi:=nextintreg;
inc(nextintreg);
end;
end
else
begin
nextintreg := R_11;
hp.paraloc.loc:=LOC_REFERENCE;
hp.paraloc.reference.index:=stack_pointer_reg;
hp.paraloc.reference.offset:=stack_offset;
if not is_64bit then
inc(stack_offset,4)
else
inc(stack_offset,8);
end;
end;
LOC_FPUREGISTER:
begin
if hp.paratyp in [vs_var,vs_out] then
begin
if nextintreg<=R_10 then
begin
hp.paraloc.size:=OS_ADDR;
hp.paraloc.loc:=LOC_REGISTER;
hp.paraloc.register:=nextintreg;
inc(nextintreg);
end
else
begin
{!!!!!!!}
hp.paraloc.size:=def_cgsize(hp.paratype.def);
internalerror(2002071006);
end;
end
else if nextfloatreg<=R_F10 then
begin
hp.paraloc.size:=def_cgsize(hp.paratype.def);
hp.paraloc.loc:=LOC_FPUREGISTER;
hp.paraloc.register:=nextfloatreg;
inc(nextfloatreg);
end
else
begin
{!!!!!!!}
hp.paraloc.size:=def_cgsize(hp.paratype.def);
internalerror(2002071004);
end;
end;
LOC_REFERENCE:
begin
hp.paraloc.size:=OS_ADDR;
if push_addr_param(hp.paratype.def,p.proccalloption in [pocall_cdecl,pocall_cppdecl]) or (hp.paratyp in [vs_var,vs_out]) then
begin
if nextintreg<=R_10 then
begin
hp.paraloc.loc:=LOC_REGISTER;
hp.paraloc.register:=nextintreg;
inc(nextintreg);
end
else
begin
hp.paraloc.loc:=LOC_REFERENCE;
hp.paraloc.reference.index:=stack_pointer_reg;
hp.paraloc.reference.offset:=stack_offset;
inc(stack_offset,4);
end;
end
else
begin
hp.paraloc.loc:=LOC_REFERENCE;
hp.paraloc.reference.index:=stack_pointer_reg;
hp.paraloc.reference.offset:=stack_offset;
inc(stack_offset,hp.paratype.def.size);
end;
end;
else
internalerror(2002071002);
end;
hp:=tparaitem(hp.previous);
end;
end;
function tcpuparamanager.getfuncretparaloc(p : tabstractprocdef) : tparalocation;
begin
case p.returndef.typ of
orddef,
enumdef:
begin
getfuncretparaloc.loc:=LOC_REGISTER;
getfuncretparaloc.register:=R_3;
getfuncretparaloc.size:=def_cgsize(p.returndef);
if getfuncretparaloc.size in [OS_S64,OS_64] then
getfuncretparaloc.register64.reghi:=R_4;
end;
floatdef:
begin
getfuncretparaloc.loc:=LOC_FPUREGISTER;
getfuncretparaloc.register:=R_F1;
getfuncretparaloc.size:=def_cgsize(p.returndef);
end;
pointerdef,
formaldef,
classrefdef,
recorddef,
objectdef,
stringdef,
procvardef,
filedef,
arraydef,
errordef:
begin
getfuncretparaloc.loc:=LOC_REGISTER;
getfuncretparaloc.register:=R_3;
getfuncretparaloc.size:=OS_ADDR;
end;
else
internalerror(2002090903);
end;
end;
begin
paramanager:=tcpuparamanager.create;
end.

43
compiler/alpha/cpupi.pas
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@ -1,43 +0,0 @@
{
Copyright (c) 2002 by Florian Klaempfl
This unit contains the CPU specific part of tprocinfo
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit contains the CPU specific part of tprocinfo.
}
unit cpupi;
{$i fpcdefs.inc}
interface
uses
cgbase;
type
talphaprocinfo = class(tprocinfo)
end;
implementation
begin
cprocinfo:=talphaprocinfo;
end.

51
compiler/alpha/cputarg.pas
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@ -1,51 +0,0 @@
{
Copyright (c) 2001-2002 by Peter Vreman
Includes the powerpc dependent target units
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit cputarg;
{$i fpcdefs.inc}
interface
implementation
uses
systems { prevent a syntax error when nothing is included }
{**************************************
Targets
**************************************}
{$ifndef NOTARGETLINUX}
,t_linux
{$endif}
{**************************************
Assemblers
**************************************}
{$ifndef NOAGAXPGAS}
,agaxpgas
{$endif}
;
end.

0
compiler/alpha/radirect.pas
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65
compiler/alpha/rasm.pas
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@ -1,65 +0,0 @@
{
Copyright (c) 1998-2002 by The Free Pascal Team
This unit does the parsing process for the inline assembler
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit does the parsing process for the inline assembler.
}
Unit Rasm;
{$i fpcdefs.inc}
Interface
uses
node;
{
This routine is called to parse the instructions in assembler
blocks. It returns a complete list of directive and instructions
}
function assemble: tnode;
Implementation
uses
{ common }
cutils,cclasses,
{ global }
globtype,globals,verbose,
systems,
{ aasm }
cpubase,aasmbase,aasmtai,aasmdata,aasmcpu,
{ symtable }
symconst,symbase,symtype,symsym,symtable,
{ pass 1 }
nbas,
{ parser }
scanner
// ,rautils
;
function assemble : tnode;
begin
end;
Begin
end.

69
compiler/alpha/rgcpu.pas
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@ -1,69 +0,0 @@
{
Copyright (c) 1998-2002 by Florian Klaempfl
This unit implements the powerpc specific class for the register
allocator
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit rgcpu;
{$i fpcdefs.inc}
interface
uses
aasmbase,aasmtai,aasmdata,
cpubase,
rgobj;
type
trgcpu = class(trgobj)
function getcpuregisterint(list: TAsmList; reg: tregister): tregister; override;
procedure ungetregisterint(list: TAsmList; reg: tregister); override;
end;
implementation
uses
cgobj;
function trgcpu.getcpuregisterint(list: TAsmList; reg: tregister): tregister;
begin
if reg = R_0 then
begin
cg.a_reg_alloc(list,reg);
result := reg;
end
else result := inherited getcpuregisterint(list,reg);
end;
procedure trgcpu.ungetregisterint(list: TAsmList; reg: tregister);
begin
if reg = R_0 then
cg.a_reg_dealloc(list,reg)
else
inherited ungetregisterint(list,reg);
end;
initialization
rg := trgcpu.create;
end.

216
compiler/alpha/symcpu.pas
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@ -1,216 +0,0 @@
{
Copyright (c) 2014 by Florian Klaempfl
Symbol table overrides for Alpha
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit symcpu;
{$i fpcdefs.inc}
interface
uses
symtype,symdef,symsym;
type
{ defs }
tcpufiledef = class(tfiledef)
end;
tcpufiledefclass = class of tcpufiledef;
tcpuvariantdef = class(tvariantdef)
end;
tcpuvariantdefclass = class of tcpuvariantdef;
tcpuformaldef = class(tformaldef)
end;
tcpuformaldefclass = class of tcpuformaldef;
tcpuforwarddef = class(tforwarddef)
end;
tcpuforwarddefclass = class of tcpuforwarddef;
tcpuundefineddef = class(tundefineddef)
end;
tcpuundefineddefclass = class of tcpuundefineddef;
tcpuerrordef = class(terrordef)
end;
tcpuerrordefclass = class of tcpuerrordef;
tcpupointerdef = class(tpointerdef)
end;
tcpupointerdefclass = class of tcpupointerdef;
tcpurecorddef = class(trecorddef)
end;
tcpurecorddefclass = class of tcpurecorddef;
tcpuimplementedinterface = class(timplementedinterface)
end;
tcpuimplementedinterfaceclass = class of tcpuimplementedinterface;
tcpuobjectdef = class(tobjectdef)
end;
tcpuobjectdefclass = class of tcpuobjectdef;
tcpuclassrefdef = class(tclassrefdef)
end;
tcpuclassrefdefclass = class of tcpuclassrefdef;
tcpuarraydef = class(tarraydef)
end;
tcpuarraydefclass = class of tcpuarraydef;
tcpuorddef = class(torddef)
end;
tcpuorddefclass = class of tcpuorddef;
tcpufloatdef = class(tfloatdef)
end;
tcpufloatdefclass = class of tcpufloatdef;
tcpuprocvardef = class(tprocvardef)
end;
tcpuprocvardefclass = class of tcpuprocvardef;
tcpuprocdef = class(tprocdef)
end;
tcpuprocdefclass = class of tcpuprocdef;
tcpustringdef = class(tstringdef)
end;
tcpustringdefclass = class of tcpustringdef;
tcpuenumdef = class(tenumdef)
end;
tcpuenumdefclass = class of tcpuenumdef;
tcpusetdef = class(tsetdef)
end;
tcpusetdefclass = class of tcpusetdef;
{ syms }
tcpulabelsym = class(tlabelsym)
end;
tcpulabelsymclass = class of tcpulabelsym;
tcpuunitsym = class(tunitsym)
end;
tcpuunitsymclass = class of tcpuunitsym;
tcpuprogramparasym = class(tprogramparasym)
end;
tcpuprogramparasymclass = class(tprogramparasym);
tcpunamespacesym = class(tnamespacesym)
end;
tcpunamespacesymclass = class of tcpunamespacesym;
tcpuprocsym = class(tprocsym)
end;
tcpuprocsymclass = class of tcpuprocsym;
tcputypesym = class(ttypesym)
end;
tcpuypesymclass = class of tcputypesym;
tcpufieldvarsym = class(tfieldvarsym)
end;
tcpufieldvarsymclass = class of tcpufieldvarsym;
tcpulocalvarsym = class(tlocalvarsym)
end;
tcpulocalvarsymclass = class of tcpulocalvarsym;
tcpuparavarsym = class(tparavarsym)
end;
tcpuparavarsymclass = class of tcpuparavarsym;
tcpustaticvarsym = class(tstaticvarsym)
end;
tcpustaticvarsymclass = class of tcpustaticvarsym;
tcpuabsolutevarsym = class(tabsolutevarsym)
end;
tcpuabsolutevarsymclass = class of tcpuabsolutevarsym;
tcpupropertysym = class(tpropertysym)
end;
tcpupropertysymclass = class of tcpupropertysym;
tcpuconstsym = class(tconstsym)
end;
tcpuconstsymclass = class of tcpuconstsym;
tcpuenumsym = class(tenumsym)
end;
tcpuenumsymclass = class of tcpuenumsym;
tcpusyssym = class(tsyssym)
end;
tcpusyssymclass = class of tcpusyssym;
const
pbestrealtype : ^tdef = @s64floattype;
implementation
begin
{ used tdef classes }
cfiledef:=tcpufiledef;
cvariantdef:=tcpuvariantdef;
cformaldef:=tcpuformaldef;
cforwarddef:=tcpuforwarddef;
cundefineddef:=tcpuundefineddef;
cerrordef:=tcpuerrordef;
cpointerdef:=tcpupointerdef;
crecorddef:=tcpurecorddef;
cimplementedinterface:=tcpuimplementedinterface;
cobjectdef:=tcpuobjectdef;
cclassrefdef:=tcpuclassrefdef;
carraydef:=tcpuarraydef;
corddef:=tcpuorddef;
cfloatdef:=tcpufloatdef;
cprocvardef:=tcpuprocvardef;
cprocdef:=tcpuprocdef;
cstringdef:=tcpustringdef;
cenumdef:=tcpuenumdef;
csetdef:=tcpusetdef;
{ used tsym classes }
clabelsym:=tcpulabelsym;
cunitsym:=tcpuunitsym;
cprogramparasym:=tcpuprogramparasym;
cnamespacesym:=tcpunamespacesym;
cprocsym:=tcpuprocsym;
ctypesym:=tcputypesym;
cfieldvarsym:=tcpufieldvarsym;
clocalvarsym:=tcpulocalvarsym;
cparavarsym:=tcpuparavarsym;
cstaticvarsym:=tcpustaticvarsym;
cabsolutevarsym:=tcpuabsolutevarsym;
cpropertysym:=tcpupropertysym;
cconstsym:=tcpuconstsym;
cenumsym:=tcpuenumsym;
csyssym:=tcpusyssym;
end.

42
compiler/alpha/tgcpu.pas
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@ -1,42 +0,0 @@
{
Copyright (C) 1998-2000 by Florian Klaempfl
This unit handles the temporary variables stuff for Alpha
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{
This unit handles the temporary variables stuff for Alpha.
}
unit tgcpu;
{$i fpcdefs.inc}
interface
uses
tgobj;
type
ttgalpha = class(ttgobj)
end;
implementation
begin
tg:=ttgalpha.create;
end.

2265
compiler/i386/csopt386.pas
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372
compiler/i386/rropt386.pas
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@ -1,372 +0,0 @@
{
Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
development team
This unit contains register renaming functionality
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit rropt386;
{$i fpcdefs.inc}
interface
uses aasmbase,aasmtai,aasmdata,aasmcpu;
procedure doRenaming(asml: TAsmList; first, last: tai);
implementation
uses
{$ifdef replaceregdebug}cutils,{$endif}
verbose,globals,cpubase,daopt386,csopt386,rgobj,
cgbase,cgutils,cgobj;
function canBeFirstSwitch(p: taicpu; supreg: tsuperregister): boolean;
{ checks whether an operation on reg can be switched to another reg without an }
{ additional mov, e.g. "addl $4,%reg1" can be changed to "leal 4(%reg1),%reg2" }
begin
canBeFirstSwitch := false;
case p.opcode of
A_MOV,A_MOVZX,A_MOVSX,A_LEA:
canBeFirstSwitch :=
(p.oper[1]^.typ = top_reg) and
(getsupreg(p.oper[1]^.reg) = supreg);
A_IMUL:
canBeFirstSwitch :=
(p.ops >= 2) and
(p.oper[0]^.typ = top_const) and
(getsupreg(p.oper[p.ops-1]^.reg) = supreg) and
(not pTaiprop(p.optinfo)^.FlagsUsed);
A_INC,A_DEC:
canBeFirstSwitch :=
(p.oper[0]^.typ = top_reg) and
(p.opsize = S_L) and
(not pTaiprop(p.optinfo)^.FlagsUsed);
A_SUB,A_ADD:
canBeFirstSwitch :=
(p.oper[1]^.typ = top_reg) and
(p.opsize = S_L) and
(getsupreg(p.oper[1]^.reg) = supreg) and
(p.oper[0]^.typ <> top_ref) and
((p.opcode <> A_SUB) or
(p.oper[0]^.typ = top_const)) and
(not pTaiprop(p.optinfo)^.FlagsUsed);
A_SHL:
canBeFirstSwitch :=
(p.opsize = S_L) and
(p.oper[1]^.typ = top_reg) and
(getsupreg(p.oper[1]^.reg) = supreg) and
(p.oper[0]^.typ = top_const) and
(p.oper[0]^.val in [1,2,3]) and
(not pTaiprop(p.optinfo)^.FlagsUsed);
end;
end;
procedure switchReg(var reg: tregister; reg1, reg2: tsuperregister);
var
supreg: tsuperregister;
begin
if (reg = NR_NO) or
(getregtype(reg) <> R_INTREGISTER) then
exit;
supreg := getsupreg(reg);
if (supreg = reg1) then
setsupreg(reg,reg2)
else if (supreg = reg2) then
setsupreg(reg,reg1);
end;
procedure switchOp(var op: toper; reg1, reg2: tsuperregister);
begin
case op.typ of
top_reg:
switchReg(op.reg,reg1,reg2);
top_ref:
begin
switchReg(op.ref^.base,reg1,reg2);
switchReg(op.ref^.index,reg1,reg2);
end;
end;
end;
procedure doSwitchReg(hp: taicpu; reg1,reg2: tsuperregister);
var
opCount: longint;
begin
for opCount := 0 to hp.ops-1 do
switchOp(hp.oper[opCount]^,reg1,reg2);
end;
procedure doFirstSwitch(p: taicpu; reg1, reg2: tsuperregister);
var
tmpRef: treference;
begin
case p.opcode of
A_MOV,A_MOVZX,A_MOVSX,A_LEA:
begin
changeOp(p.oper[1]^,reg1,reg2);
changeOp(p.oper[0]^,reg2,reg1);
end;
A_IMUL:
begin
p.ops := 3;
p.loadreg(2,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
changeOp(p.oper[1]^,reg2,reg1);
end;
A_INC,A_DEC:
begin
reference_reset(tmpref,1);
tmpref.base := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
case p.opcode of
A_INC:
tmpref.offset := 1;
A_DEC:
tmpref.offset := -1;
end;
p.ops := 2;
p.opcode := A_LEA;
p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
p.loadref(0,tmpref);
end;
A_SUB,A_ADD:
begin
reference_reset(tmpref,1);
tmpref.base := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
case p.oper[0]^.typ of
top_const:
begin
tmpref.offset := longint(p.oper[0]^.val);
if p.opcode = A_SUB then
tmpref.offset := - tmpRef.offset;
end;
top_ref:
if (p.oper[0]^.ref^.refaddr=addr_full) then
tmpref.symbol := p.oper[0]^.ref^.symbol
else
internalerror(200402263);
top_reg:
begin
{ "addl %reg2,%reg1" must become "leal (%reg1,%reg1),%reg2" }
{ since at this point reg1 holds the value that reg2 would }
{ otherwise contain }
tmpref.index := p.oper[0]^.reg;
if (getsupreg(tmpref.index)=reg2) then
setsupreg(tmpref.index,reg1);
tmpref.scalefactor := 1;
end;
else internalerror(200010031);
end;
p.opcode := A_LEA;
p.loadref(0,tmpref);
p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
end;
A_SHL:
begin
reference_reset(tmpref,2);
tmpref.index := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
tmpref.scalefactor := 1 shl p.oper[0]^.val;
p.opcode := A_LEA;
p.loadref(0,tmpref);
p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
end;
else internalerror(200010032);
end;
end;
function switchRegs(asml: TAsmList; reg1, reg2: tsuperregister; start: tai): Boolean;
{ change movl %reg1,%reg2 ... bla ... to ... bla with reg1 and reg2 switched }
var
endP, hp, lastreg1,lastreg2: tai;
switchDone, switchLast, tmpResult, sequenceEnd, reg1Modified, reg2Modified: boolean;
reg1StillUsed, reg2StillUsed, isInstruction: boolean;
begin
switchRegs := false;
tmpResult := true;
sequenceEnd := false;
reg1Modified := false;
reg2Modified := false;
switchLast := false;
endP := start;
while tmpResult and not sequenceEnd do
begin
tmpResult :=
getNextInstruction(endP,endP);
If tmpResult and
not pTaiprop(endp.optinfo)^.canBeRemoved then
begin
{ if the newReg gets stored back to the oldReg, we can change }
{ "mov %oldReg,%newReg; <operations on %newReg>; mov %newReg, }
{ %oldReg" to "<operations on %oldReg>" }
switchLast := storeBack(start,endP,reg1,reg2);
reg1StillUsed := reg1 in pTaiprop(endp.optinfo)^.usedregs;
reg2StillUsed := reg2 in pTaiprop(endp.optinfo)^.usedregs;
isInstruction := endp.typ = ait_instruction;
sequenceEnd :=
switchLast or
{ if both registers are released right before an instruction }
{ that contains hardcoded regs, it's ok too }
(not reg1StillUsed and not reg2StillUsed) or
{ no support for (i)div, mul and imul with hardcoded operands }
(((not isInstruction) or
noHardCodedRegs(taicpu(endP),reg1,reg2)) and
(not reg1StillUsed or
(isInstruction and findRegDealloc(reg1,endP) and
regLoadedWithNewValue(reg1,false,taicpu(endP)))) and
(not reg2StillUsed or
(isInstruction and findRegDealloc(reg2,endP) and
regLoadedWithNewValue(reg2,false,taicpu(endP)))));
{ we can't switch reg1 and reg2 in something like }
{ movl %reg1,%reg2 }
{ movl (%reg2),%reg2 }
{ movl 4(%reg1),%reg1 }
if reg2Modified and not(reg1Modified) and
regReadByInstruction(reg1,endP) then
begin
tmpResult := false;
break
end;
if not reg1Modified then
begin
reg1Modified := regModifiedByInstruction(reg1,endP);
if reg1Modified and not canBeFirstSwitch(taicpu(endP),reg1) then
begin
tmpResult := false;
break;
end;
end;
if not reg2Modified then
reg2Modified := regModifiedByInstruction(reg2,endP);
tmpResult :=
((not isInstruction) or
(NoHardCodedRegs(taicpu(endP),reg1,reg2) and
RegSizesOk(reg1,reg2,taicpu(endP))));
if sequenceEnd then
break;
tmpResult :=
tmpresult and
(endp.typ <> ait_label) and
((not isInstruction) or
(not taicpu(endp).is_jmp));
end;
end;
if tmpResult and sequenceEnd then
begin
switchRegs := true;
reg1Modified := false;
reg2Modified := false;
lastreg1 := start;
lastreg2 := start;
getNextInstruction(start,hp);
while hp <> endP do
begin
if (not pTaiprop(hp.optinfo)^.canberemoved) and
(hp.typ = ait_instruction) then
begin
switchDone := false;
if not reg1Modified then
begin
reg1Modified := regModifiedByInstruction(reg1,hp);
if reg1Modified then
begin
doFirstSwitch(taicpu(hp),reg1,reg2);
switchDone := true;
end;
end;
if not switchDone then
if reg1Modified then
doSwitchReg(taicpu(hp),reg1,reg2)
else
doReplaceReg(taicpu(hp),reg2,reg1);
end;
if regininstruction(reg1,hp) then
lastreg1 := hp;
if regininstruction(reg2,hp) then
lastreg2 := hp;
getNextInstruction(hp,hp);
end;
if switchLast then
begin
lastreg1 := hp;
lastreg2 := hp;
{ this is in case of a storeback, make sure the same size of register }
{ contents as the initial move is transfered }
doSwitchReg(taicpu(hp),reg1,reg2);
if taicpu(hp).opsize <> taicpu(start).opsize then
begin
taicpu(hp).opsize := taicpu(start).opsize;
taicpu(hp).oper[0]^.reg := taicpu(start).oper[0]^.reg;
taicpu(hp).oper[1]^.reg := taicpu(start).oper[1]^.reg;
end;
end
else
getLastInstruction(hp,hp);
allocRegBetween(asmL,newreg(R_INTREGISTER,reg1,R_SUBWHOLE),start,lastreg1,
ptaiprop(start.optinfo)^.usedregs);
allocRegBetween(asmL,newreg(R_INTREGISTER,reg2,R_SUBWHOLE),start,lastreg2,
ptaiprop(start.optinfo)^.usedregs);
end;
end;
procedure doRenaming(asml: TAsmList; first, last: tai);
var
p: tai;
begin
p := First;
SkipHead(p);
while p <> last do
begin
case p.typ of
ait_instruction:
begin
case taicpu(p).opcode of
A_MOV:
begin
if not(pTaiprop(p.optinfo)^.canBeRemoved) and
(taicpu(p).oper[0]^.typ = top_reg) and
(taicpu(p).oper[1]^.typ = top_reg) and
(taicpu(p).opsize = S_L) and
(getsupreg(taicpu(p).oper[0]^.reg) in ([RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI])) and
(getsupreg(taicpu(p).oper[1]^.reg) in ([RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI])) then
if switchRegs(asml,getsupreg(taicpu(p).oper[0]^.reg),
getsupreg(taicpu(p).oper[1]^.reg),p) then
begin
pTaiprop(p.optinfo)^.canBeRemoved := true;
end;
end;
end;
end;
end;
getNextInstruction(p,p);
end;
end;
End.

287
compiler/ia64/aasmcpu.pas
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@ -1,287 +0,0 @@
{
Copyright (c) 2000-2006 by Florian Klaempfl
Contains the assembler object for the ia64
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit aasmcpu;
{$i fpcdefs.inc}
interface
uses
globals,verbose,
aasmbase,aasmtai,
cpubase,
cgutils;
type
pairegalloc = ^tairegalloc;
tairegalloc = class(tai)
allocation : boolean;
reg : tregister;
constructor alloc(r : tregister);
constructor dealloc(r : tregister);
end;
{ Types of operand }
toptype=(top_none,top_reg,top_ref,top_const,top_symbol,top_qp);
paicpu = ^taicpu;
taicpu = class(tai)
is_jmp : boolean; { is this instruction a jump? (needed for optimizer) }
opcode : tasmop;
ops : array[0..4] of longint;
oper : longint;
qp : tqp;
ldsttype : tldsttype;
hint : thint;
{ ALU instructions }
{ A1,A9: integer ALU }
constructor op_reg_reg_reg(op : tasmop;const r1,r2,r3 : tregister);
{ A2,A10: shift left and add }
constructor op_reg_reg_const_reg(_qp : tqp;op : tasmop;
const r1,r2 : tregister;i : byte;const r3 : tregister);
{ A3,A4,A5: integer ALU - imm.,register }
constructor op_reg_const_reg(_qp : tqp;op : tasmop;
const r1 : tregister;i : longint;const r3 : tregister);
{ A6,A7: integer compare - register,register }
constructor op_preg_preg_reg_reg(_qp : tqp;op : tasmop;
cond : tasmcond;p1,p2 : tqp;const r2,r3 : tregister);
{ A8: integer compare - imm.,register }
constructor op_preg_preg_const_reg(_qp : tqp;op : tasmop;
cond : tasmcond;p1,p2 : tqp;i : longint;const r3 : tregister);
(*!!!!!!!
{ multimedia shift and multiply }
constructor op_reg_reg_reg_const(_qp : tqp;
{ multimedia mux }
constructor op_reg_reg_mbtype(_qp : tqp;
{ multimedia shift fixed }
constructor op_reg_reg_const(_qp : tqp;
{ div. }
constructor op_reg_reg(_qp : tqp;
{ mm extract }
constructor op_reg_reg_const_const(_qp : tqp;
{ zero and deposit imm }
constructor op_reg_const_const_const(_qp : tqp;
{ deposit imm }
constructor op_reg_const_reg_const_const(_qp : tqp;
{ deposit }
constructor op_reg_reg_reg_const_const(_qp : tqp;
{ test bit }
{ !!!! here we need also to take care of the postfix }
constructor op_preg_preg_reg_const(_qp : tqp;
{ test NaT }
{ !!!! here we need also to take care of the postfix }
constructor op_preg_preg_reg(_qp : tqp;
{ -------- here are some missed ----------- }
*)
{ M1: integer load }
{ M4: integer store }
{ M6: floating-point load }
{ M9: floating-point store }
constructor op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;ref : treference);
{ M2: integer load incremented by register }
{ M7: floating-point load incremented by register }
constructor op_reg_ref_reg(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;const ref : treference;
const r2 : tregister);
{ M3: integer load increment by imm. }
{ M5: integer store increment by imm. }
{ M8: floating-point load increment by imm. }
{ M10: floating-point store increment by imm. }
constructor op_reg_ref_const(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;ref : treference;i : longint);
{ M11: floating-point load pair}
constructor op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1,r2 : tregister;ref : treference);
{ M12: floating-point load pair increment by imm. }
constructor op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1,r2 : tregister;ref : treference;i : longint);
{ X1: break/nop }
constructor op_const62(_qp : tqp;op : tasmop;i : int64);
{ X2: move imm64 }
constructor op_reg_const64(_qp : tqp;op : tasmop;const r1 : tregister;
i : int64);
end;
{ the following objects are special for the ia64 }
{ they decribe a stop and the bundles }
paistop = ^taistop;
taistop = class(tai)
constructor init;
end;
{ a second underscro indicates a stop }
tbundletemplate = (but_none,but_mii,but_mii_,
but_mi_i,but_mi_i_,but_mlx,but_mlx_,
but_mmi,but_mmi_,but_m_mi,but_m_mi_,
but_mfi,but_mfi_,but_mmf,but_mmf_,
but_mif,but_mib_,but_mbb,but_mbb_,
but_bbb,but_bbb_,but_mmb,but_mmb_,
but_mfb,but_mfb_);
paibundle = ^taibundle;
taibundle = class(tai)
template : tbundletemplate;
instructions : array[0..1] of paicpu;
end;
implementation
{*****************************************************************************
TaiStop
*****************************************************************************}
constructor taistop.init;
begin
inherited create;
typ:=ait_stop;
end;
{*****************************************************************************
TaiRegAlloc
*****************************************************************************}
constructor tairegalloc.alloc(r : tregister);
begin
inherited create;
typ:=ait_regalloc;
allocation:=true;
reg:=r;
end;
constructor tairegalloc.dealloc(r : tregister);
begin
inherited create;
typ:=ait_regalloc;
allocation:=false;
reg:=r;
end;
{*****************************************************************************
Taicpu
*****************************************************************************}
{ ALU instructions }
{ A1,A9: integer ALU }
constructor taicpu.op_reg_reg_reg(op : tasmop;const r1,r2,r3 : tregister);
begin
end;
{ A2,A10: shift left and add }
constructor taicpu.op_reg_reg_const_reg(_qp : tqp;op : tasmop;
const r1,r2 : tregister;i : byte;const r3 : tregister);
begin
end;
{ A3,A4,A5: integer ALU - imm.,register }
constructor taicpu.op_reg_const_reg(_qp : tqp;op : tasmop;
const r1 : tregister;i : longint;const r3 : tregister);
begin
end;
{ A6,A7: integer compare - register,register }
constructor taicpu.op_preg_preg_reg_reg(_qp : tqp;op : tasmop;
cond : tasmcond;p1,p2 : tqp;const r2,r3 : tregister);
begin
end;
{ A8: integer compare - imm.,register }
constructor taicpu.op_preg_preg_const_reg(_qp : tqp;op : tasmop;
cond : tasmcond;p1,p2 : tqp;i : longint;const r3 : tregister);
begin
end;
{ M1: integer load }
{ M4: integer store }
{ M6: floating-point load }
{ M9: floating-point store }
constructor taicpu.op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;ref : treference);
begin
end;
{ M2: integer load incremented by register }
{ M7: floating-point load incremented by register }
constructor taicpu.op_reg_ref_reg(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;const ref : treference;
const r2 : tregister);
begin
end;
{ M3: integer load increment by imm. }
{ M5: integer store increment by imm. }
{ M8: floating-point load increment by imm. }
{ M10: floating-point store increment by imm. }
constructor taicpu.op_reg_ref_const(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1 : tregister;ref : treference;i : longint);
begin
end;
{ M11: floating-point load pair}
constructor taicpu.op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1,r2 : tregister;ref : treference);
begin
end;
{ M12: floating-point load pair increment by imm. }
constructor taicpu.op_reg_ref(_qp : tqp;op : tasmop;postfix : tldsttype;
_hint : thint;const r1,r2 : tregister;ref : treference;i : longint);
begin
end;
{ X1: break/nop }
constructor taicpu.op_const62(_qp : tqp;op : tasmop;i : int64);
{ X2: move imm64 }
begin
end;
constructor taicpu.op_reg_const64(_qp : tqp;op : tasmop;const r1 : tregister;
i : int64);
begin
end;
end.

150
compiler/ia64/cpubase.pas
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@ -1,150 +0,0 @@
{
Copyright (C) 2000-2006 by Florian Klaempfl
this unit implements the base types for the iA-64 architecture
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit cpubase;
interface
uses
cutils,
globals,
systems,
cpuinfo,
cgbase;
type
tasmop = (A_ADD,A_SUB,A_ADDP4,A_AND,A_ANDCM,A_OR,A_XOR,A_SHLADD,
A_SHLADDP4,A_ADDS,A_ADDL,A_CMP,A_CMP4,A_PADD1,A_PADD2,
A_PADD4,A_PSUB1,A_PSUB2,A_PSUB4,A_PAVG1,A_PAVG2,A_PAVGSUB1,
A_PAVGSUB2,A_PCMP1,A_PCMP2,A_PCMP4,A_PSHLADD2,A_PSHRADD2,
A_PMPY2,A_MIX1,A_MIX2,A_MIX4,A_PACK2,A_PACK4,A_UNPACK2,
A_UNPACK4,A_PMIN1,A_PMAX1,A_PMIN2,A_PMAX2,A_PSAD1,A_MUX1,
A_MUX2,A_PSHR2,A_PSHR4,A_SHR,A_PSHL2,A_SHL4,A_SHL,
A_POPCNT,A_SHRP,A_EXTR,A_DEP,A_TBIT,A_TNAT,A_BREAK,
A_NOP,A_CHK,A_MOV,A_ZX1,A_ZX2,A_ZXT4,A_SXT1,A_SXT2,A_SXT4,
A_CXZ1,A_CZX2,A_LD1,A_LD2,A_LD4,A_LD8,A_ST1,A_ST2,A_ST4,
A_ST8,A_LDFS,A_LDFD,A_LDF8,A_LDFE,A_LDF,A_STFS,A_STFD,A_STF8,
A_STFE,A_STF,A_LDFPS,A_LDFPD,A_LDFP8,A_LFETCH,A_CMPXCHG1,
A_CMPXCHG2,A_CMPXHG4,A_CMPXCHG8,A_XCHG1,A_XCHG2,A_XCHG4,
A_XCHG8,A_FETCHADD4,A_FETCHADD8,A_SETF,A_GETF,
A_INVALA,A_MF,A_SRLZ,A_SYNC,A_FLUSHRS,A_FC,A_ALLOC,A_SUM,
A_RUM,A_BR,A_CLRRRB,A_FMA,A_FPMA,A_FMS,A_FPMS,A_FNMA,A_FPNMA,
A_XMA,A_FSELECT,A_FCLASS,A_FRCPA,A_FPRCPA,A_FRSQRTA,
A_FPRSQRTA,A_FMIN,A_FMAX,A_FAMIN,A_FAMAX,A_FPMIN,A_FPMAX,
A_FPAMIN,A_FPAMAX,A_FPCMP,A_FMERGE,A_FMIX,A_FSXT,A_FPACK,
A_FSWAP,A_FAND,A_FANDCM,A_FOR,A_FXOR,A_FPMERGE,A_FCVT,
A_FPCVT,A_FSETC,A_FCLRT,A_FCHKF,A_MOVL);
Const
firstop = low(tasmop);
lastop = high(tasmop);
type
TAsmCond = (C_NONE,C_LT,C_LTU,C_EQ,C_LT_UNC,C_LTU_UNC,C_EQ_UNC,
C_EQ_AND,C_EQ_OR,C_EQ_OR_ANDCM,C_NE_AND,C_NE_OR);
THint = (H_NONE,H_NT1,H_NT2,H_NTA);
TLdStType = (LST_NONE,LST_S,LST_A,LSR_SA,LST_BIAS,LST_ACQ,LST_C_CLR,
LST_FILL,LST_C_NC,LST_C_CLR_ACQ,LST_REL,
LST_SPILL);
{*****************************************************************************
Flags
*****************************************************************************}
type
TResFlags = (F_NONE,F_LT,F_LTU,F_EQ,F_LT_UNC,F_LTU_UNC,F_EQ_UNC,
F_EQ_AND,F_EQ_OR,F_EQ_OR_ANDCM,F_NE_AND,F_NE_OR);
Type
TRegister = (R_NO, { R_NO is Mandatory, signifies no register }
R_0,R_1,R_2,R_3,R_4,R_5,R_6,R_7,R_8,R_9,
R_10,R_11,R_12,R_13,R_14,R_15,R_16,R_17,R_18,R_19,
R_20,R_21,R_22,R_23,R_24,R_25,R_26,R_27,R_28,R_29,
R_30,R_31,
R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,
R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,
R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
R_F30,R_F31);
TRegisterset = Set of TRegister;
{ -1 indicates no qualifying prediction }
tqp = -1..63;
const
qp_none : tqp = -1;
{ Constants describing the registers }
Const
intregs = [R_0..R_31];
fpuregs = [R_F0..R_F31];
mmregs = [];
maxvarregs = 128;
maxfpuvarregs = 128;
max_operands = 4;
{*****************************************************************************
Default generic sizes
*****************************************************************************}
{ Defines the default address size for a processor, }
OS_ADDR = OS_64;
{ the natural int size for a processor,
has to match osuinttype/ossinttype as initialized in psystem }
OS_INT = OS_64;
OS_SINT = OS_S64;
{ the maximum float size for a processor, }
OS_FLOAT = OS_F80;
{ the size of a vector register for a processor }
OS_VECTOR = OS_M128;
{*****************************************************************************
GCC /ABI linking information
*****************************************************************************}
{# Registers which must be saved when calling a routine declared as
cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
saved should be the ones as defined in the target ABI and / or GCC.
This value can be deduced from CALLED_USED_REGISTERS array in the
GCC source.
}
std_saved_registers = [R_9..R_14,R_F2..R_F9];
{# Required parameter alignment when calling a routine declared as
stdcall and cdecl. The alignment value should be the one defined
by GCC or the target ABI.
The value of this constant is equal to the constant
PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
}
std_param_align = 8;
{*****************************************************************************
Opcode propeties (needed for optimizer)
*****************************************************************************}
implementation
end.

105
compiler/ia64/cpuinfo.pas
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@ -1,105 +0,0 @@
{
Copyright (c) 1998-2006 by Florian Klaempfl
Basic Processor information
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
Unit cpuinfo;
{$i fpcdefs.inc}
Interface
uses
globtype;
Type
bestreal = extended;
{$if FPC_FULLVERSION>20700}
bestrealrec = TExtended80Rec;
{$endif FPC_FULLVERSION>20700}
ts32real = single;
ts64real = double;
ts80real = extended;
ts128real = type extended;
ts64comp = type extended;
pbestreal=^bestreal;
{ possible supported processors for this target }
tcputype =
(cpu_none,
cpu_itanium
);
tfputype =
(fpu_none,
fpu_itanium
);
tcontrollertype =
(ct_none
);
Const
{ Is there support for dealing with multiple microcontrollers available }
{ for this platform? }
ControllerSupport = false;
{ We know that there are fields after sramsize
but we don't care about this warning }
{$PUSH}
{$WARN 3177 OFF}
embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
(
(controllertypestr:''; controllerunitstr:''; flashbase:0; flashsize:0; srambase:0; sramsize:0));
{$POP}
{ calling conventions supported by the code generator }
supported_calling_conventions : tproccalloptions = [
pocall_internproc,
pocall_stdcall,
pocall_cdecl,
pocall_cppdecl
];
cputypestr : array[tcputype] of string[10] = ('',
'ITANIUM'
);
fputypestr : array[tfputype] of string[6] = ('',
'ITANIUM'
);
{ Supported optimizations, only used for information }
supported_optimizerswitches = [cs_opt_peephole,cs_opt_regvar,cs_opt_stackframe,
cs_opt_asmcse,cs_opt_loopunroll,cs_opt_uncertain,
cs_opt_nodecse];
level1optimizerswitches = [cs_opt_level1,cs_opt_peephole];
level2optimizerswitches = level1optimizerswitches +
[cs_opt_level2,cs_opt_regvar,cs_opt_stackframe,cs_opt_asmcse,cs_opt_nodecse];
level3optimizerswitches = level2optimizerswitches + [cs_opt_level3{,cs_opt_loopunroll}];
level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
Implementation
end.

268
compiler/ia64/ia64reg.dat
View File

@ -1,268 +0,0 @@
;
; iA-64 registers
; This file is generate with help of fpc/compiler/utils/gia64reg,
; please try to use this generator before you do error prone and tedious
; editing by hand
;
; layout
; <name>,<type>,<value>,<stdname>,<gasname>
;
NO,$00,$00,INVALID,INVALID
R0,$01,0,r0,r0
R1,$01,1,r1,r1
R2,$01,2,r2,r2
R3,$01,3,r3,r3
R4,$01,4,r4,r4
R5,$01,5,r5,r5
R6,$01,6,r6,r6
R7,$01,7,r7,r7
R8,$01,8,r8,r8
R9,$01,9,r9,r9
R10,$01,10,r10,r10
R11,$01,11,r11,r11
R12,$01,12,r12,r12
R13,$01,13,r13,r13
R14,$01,14,r14,r14
R15,$01,15,r15,r15
R16,$01,16,r16,r16
R17,$01,17,r17,r17
R18,$01,18,r18,r18
R19,$01,19,r19,r19
R20,$01,20,r20,r20
R21,$01,21,r21,r21
R22,$01,22,r22,r22
R23,$01,23,r23,r23
R24,$01,24,r24,r24
R25,$01,25,r25,r25
R26,$01,26,r26,r26
R27,$01,27,r27,r27
R28,$01,28,r28,r28
R29,$01,29,r29,r29
R30,$01,30,r30,r30
R31,$01,31,r31,r31
R32,$01,32,r32,r32
R33,$01,33,r33,r33
R34,$01,34,r34,r34
R35,$01,35,r35,r35
R36,$01,36,r36,r36
R37,$01,37,r37,r37
R38,$01,38,r38,r38
R39,$01,39,r39,r39
R40,$01,40,r40,r40
R41,$01,41,r41,r41
R42,$01,42,r42,r42
R43,$01,43,r43,r43
R44,$01,44,r44,r44
R45,$01,45,r45,r45
R46,$01,46,r46,r46
R47,$01,47,r47,r47
R48,$01,48,r48,r48
R49,$01,49,r49,r49
R50,$01,50,r50,r50
R51,$01,51,r51,r51
R52,$01,52,r52,r52
R53,$01,53,r53,r53
R54,$01,54,r54,r54
R55,$01,55,r55,r55
R56,$01,56,r56,r56
R57,$01,57,r57,r57
R58,$01,58,r58,r58
R59,$01,59,r59,r59
R60,$01,60,r60,r60
R61,$01,61,r61,r61
R62,$01,62,r62,r62
R63,$01,63,r63,r63
R64,$01,64,r64,r64
R65,$01,65,r65,r65
R66,$01,66,r66,r66
R67,$01,67,r67,r67
R68,$01,68,r68,r68
R69,$01,69,r69,r69
R70,$01,70,r70,r70
R71,$01,71,r71,r71
R72,$01,72,r72,r72
R73,$01,73,r73,r73
R74,$01,74,r74,r74
R75,$01,75,r75,r75
R76,$01,76,r76,r76
R77,$01,77,r77,r77
R78,$01,78,r78,r78
R79,$01,79,r79,r79
R80,$01,80,r80,r80
R81,$01,81,r81,r81
R82,$01,82,r82,r82
R83,$01,83,r83,r83
R84,$01,84,r84,r84
R85,$01,85,r85,r85
R86,$01,86,r86,r86
R87,$01,87,r87,r87
R88,$01,88,r88,r88
R89,$01,89,r89,r89
R90,$01,90,r90,r90
R91,$01,91,r91,r91
R92,$01,92,r92,r92
R93,$01,93,r93,r93
R94,$01,94,r94,r94
R95,$01,95,r95,r95
R96,$01,96,r96,r96
R97,$01,97,r97,r97
R98,$01,98,r98,r98
R99,$01,99,r99,r99
R100,$01,100,r100,r100
R101,$01,101,r101,r101
R102,$01,102,r102,r102
R103,$01,103,r103,r103
R104,$01,104,r104,r104
R105,$01,105,r105,r105
R106,$01,106,r106,r106
R107,$01,107,r107,r107
R108,$01,108,r108,r108
R109,$01,109,r109,r109
R110,$01,110,r110,r110
R111,$01,111,r111,r111
R112,$01,112,r112,r112
R113,$01,113,r113,r113
R114,$01,114,r114,r114
R115,$01,115,r115,r115
R116,$01,116,r116,r116
R117,$01,117,r117,r117
R118,$01,118,r118,r118
R119,$01,119,r119,r119
R120,$01,120,r120,r120
R121,$01,121,r121,r121
R122,$01,122,r122,r122
R123,$01,123,r123,r123
R124,$01,124,r124,r124
R125,$01,125,r125,r125
R126,$01,126,r126,r126
R127,$01,127,r127,r127
F0,$02,0,r0,r0
F1,$02,1,r1,r1
F2,$02,2,r2,r2
F3,$02,3,r3,r3
F4,$02,4,r4,r4
F5,$02,5,r5,r5
F6,$02,6,r6,r6
F7,$02,7,r7,r7
F8,$02,8,r8,r8
F9,$02,9,r9,r9
F10,$02,10,r10,r10
F11,$02,11,r11,r11
F12,$02,12,r12,r12
F13,$02,13,r13,r13
F14,$02,14,r14,r14
F15,$02,15,r15,r15
F16,$02,16,r16,r16
F17,$02,17,r17,r17
F18,$02,18,r18,r18
F19,$02,19,r19,r19
F20,$02,20,r20,r20
F21,$02,21,r21,r21
F22,$02,22,r22,r22
F23,$02,23,r23,r23
F24,$02,24,r24,r24
F25,$02,25,r25,r25
F26,$02,26,r26,r26
F27,$02,27,r27,r27
F28,$02,28,r28,r28
F29,$02,29,r29,r29
F30,$02,30,r30,r30
F31,$02,31,r31,r31
F32,$02,32,r32,r32
F33,$02,33,r33,r33
F34,$02,34,r34,r34
F35,$02,35,r35,r35
F36,$02,36,r36,r36
F37,$02,37,r37,r37
F38,$02,38,r38,r38
F39,$02,39,r39,r39
F40,$02,40,r40,r40
F41,$02,41,r41,r41
F42,$02,42,r42,r42
F43,$02,43,r43,r43
F44,$02,44,r44,r44
F45,$02,45,r45,r45
F46,$02,46,r46,r46
F47,$02,47,r47,r47
F48,$02,48,r48,r48
F49,$02,49,r49,r49
F50,$02,50,r50,r50
F51,$02,51,r51,r51
F52,$02,52,r52,r52
F53,$02,53,r53,r53
F54,$02,54,r54,r54
F55,$02,55,r55,r55
F56,$02,56,r56,r56
F57,$02,57,r57,r57
F58,$02,58,r58,r58
F59,$02,59,r59,r59
F60,$02,60,r60,r60
F61,$02,61,r61,r61
F62,$02,62,r62,r62
F63,$02,63,r63,r63
F64,$02,64,r64,r64
F65,$02,65,r65,r65
F66,$02,66,r66,r66
F67,$02,67,r67,r67
F68,$02,68,r68,r68
F69,$02,69,r69,r69
F70,$02,70,r70,r70
F71,$02,71,r71,r71
F72,$02,72,r72,r72
F73,$02,73,r73,r73
F74,$02,74,r74,r74
F75,$02,75,r75,r75
F76,$02,76,r76,r76
F77,$02,77,r77,r77
F78,$02,78,r78,r78
F79,$02,79,r79,r79
F80,$02,80,r80,r80
F81,$02,81,r81,r81
F82,$02,82,r82,r82
F83,$02,83,r83,r83
F84,$02,84,r84,r84
F85,$02,85,r85,r85
F86,$02,86,r86,r86
F87,$02,87,r87,r87
F88,$02,88,r88,r88
F89,$02,89,r89,r89
F90,$02,90,r90,r90
F91,$02,91,r91,r91
F92,$02,92,r92,r92
F93,$02,93,r93,r93
F94,$02,94,r94,r94
F95,$02,95,r95,r95
F96,$02,96,r96,r96
F97,$02,97,r97,r97
F98,$02,98,r98,r98
F99,$02,99,r99,r99
F100,$02,100,r100,r100
F101,$02,101,r101,r101
F102,$02,102,r102,r102
F103,$02,103,r103,r103
F104,$02,104,r104,r104
F105,$02,105,r105,r105
F106,$02,106,r106,r106
F107,$02,107,r107,r107
F108,$02,108,r108,r108
F109,$02,109,r109,r109
F110,$02,110,r110,r110
F111,$02,111,r111,r111
F112,$02,112,r112,r112
F113,$02,113,r113,r113
F114,$02,114,r114,r114
F115,$02,115,r115,r115
F116,$02,116,r116,r116
F117,$02,117,r117,r117
F118,$02,118,r118,r118
F119,$02,119,r119,r119
F120,$02,120,r120,r120
F121,$02,121,r121,r121
F122,$02,122,r122,r122
F123,$02,123,r123,r123
F124,$02,124,r124,r124
F125,$02,125,r125,r125
F126,$02,126,r126,r126
F127,$02,127,r127,r127

216
compiler/ia64/symcpu.pas
View File

@ -1,216 +0,0 @@
{
Copyright (c) 2014 by Florian Klaempfl
Symbol table overrides for IA64
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit symcpu;
{$i fpcdefs.inc}
interface
uses
symtype,symdef,symsym;
type
{ defs }
tcpufiledef = class(tfiledef)
end;
tcpufiledefclass = class of tcpufiledef;
tcpuvariantdef = class(tvariantdef)
end;
tcpuvariantdefclass = class of tcpuvariantdef;
tcpuformaldef = class(tformaldef)
end;
tcpuformaldefclass = class of tcpuformaldef;
tcpuforwarddef = class(tforwarddef)
end;
tcpuforwarddefclass = class of tcpuforwarddef;
tcpuundefineddef = class(tundefineddef)
end;
tcpuundefineddefclass = class of tcpuundefineddef;
tcpuerrordef = class(terrordef)
end;
tcpuerrordefclass = class of tcpuerrordef;
tcpupointerdef = class(tpointerdef)
end;
tcpupointerdefclass = class of tcpupointerdef;
tcpurecorddef = class(trecorddef)
end;
tcpurecorddefclass = class of tcpurecorddef;
tcpuimplementedinterface = class(timplementedinterface)
end;
tcpuimplementedinterfaceclass = class of tcpuimplementedinterface;
tcpuobjectdef = class(tobjectdef)
end;
tcpuobjectdefclass = class of tcpuobjectdef;
tcpuclassrefdef = class(tclassrefdef)
end;
tcpuclassrefdefclass = class of tcpuclassrefdef;
tcpuarraydef = class(tarraydef)
end;
tcpuarraydefclass = class of tcpuarraydef;
tcpuorddef = class(torddef)
end;
tcpuorddefclass = class of tcpuorddef;
tcpufloatdef = class(tfloatdef)
end;
tcpufloatdefclass = class of tcpufloatdef;
tcpuprocvardef = class(tprocvardef)
end;
tcpuprocvardefclass = class of tcpuprocvardef;
tcpuprocdef = class(tprocdef)
end;
tcpuprocdefclass = class of tcpuprocdef;
tcpustringdef = class(tstringdef)
end;
tcpustringdefclass = class of tcpustringdef;
tcpuenumdef = class(tenumdef)
end;
tcpuenumdefclass = class of tcpuenumdef;
tcpusetdef = class(tsetdef)
end;
tcpusetdefclass = class of tcpusetdef;
{ syms }
tcpulabelsym = class(tlabelsym)
end;
tcpulabelsymclass = class of tcpulabelsym;
tcpuunitsym = class(tunitsym)
end;
tcpuunitsymclass = class of tcpuunitsym;
tcpuprogramparasym = class(tprogramparasym)
end;
tcpuprogramparasymclass = class(tprogramparasym);
tcpunamespacesym = class(tnamespacesym)
end;
tcpunamespacesymclass = class of tcpunamespacesym;
tcpuprocsym = class(tprocsym)
end;
tcpuprocsymclass = class of tcpuprocsym;
tcputypesym = class(ttypesym)
end;
tcpuypesymclass = class of tcputypesym;
tcpufieldvarsym = class(tfieldvarsym)
end;
tcpufieldvarsymclass = class of tcpufieldvarsym;
tcpulocalvarsym = class(tlocalvarsym)
end;
tcpulocalvarsymclass = class of tcpulocalvarsym;
tcpuparavarsym = class(tparavarsym)
end;
tcpuparavarsymclass = class of tcpuparavarsym;
tcpustaticvarsym = class(tstaticvarsym)
end;
tcpustaticvarsymclass = class of tcpustaticvarsym;
tcpuabsolutevarsym = class(tabsolutevarsym)
end;
tcpuabsolutevarsymclass = class of tcpuabsolutevarsym;
tcpupropertysym = class(tpropertysym)
end;
tcpupropertysymclass = class of tcpupropertysym;
tcpuconstsym = class(tconstsym)
end;
tcpuconstsymclass = class of tcpuconstsym;
tcpuenumsym = class(tenumsym)
end;
tcpuenumsymclass = class of tcpuenumsym;
tcpusyssym = class(tsyssym)
end;
tcpusyssymclass = class of tcpusyssym;
const
pbestrealtype : ^tdef = @s64floattype;
implementation
begin
{ used tdef classes }
cfiledef:=tcpufiledef;
cvariantdef:=tcpuvariantdef;
cformaldef:=tcpuformaldef;
cforwarddef:=tcpuforwarddef;
cundefineddef:=tcpuundefineddef;
cerrordef:=tcpuerrordef;
cpointerdef:=tcpupointerdef;
crecorddef:=tcpurecorddef;
cimplementedinterface:=tcpuimplementedinterface;
cobjectdef:=tcpuobjectdef;
cclassrefdef:=tcpuclassrefdef;
carraydef:=tcpuarraydef;
corddef:=tcpuorddef;
cfloatdef:=tcpufloatdef;
cprocvardef:=tcpuprocvardef;
cprocdef:=tcpuprocdef;
cstringdef:=tcpustringdef;
cenumdef:=tcpuenumdef;
csetdef:=tcpusetdef;
{ used tsym classes }
clabelsym:=tcpulabelsym;
cunitsym:=tcpuunitsym;
cprogramparasym:=tcpuprogramparasym;
cnamespacesym:=tcpunamespacesym;
cprocsym:=tcpuprocsym;
ctypesym:=tcputypesym;
cfieldvarsym:=tcpufieldvarsym;
clocalvarsym:=tcpulocalvarsym;
cparavarsym:=tcpuparavarsym;
cstaticvarsym:=tcpustaticvarsym;
cabsolutevarsym:=tcpuabsolutevarsym;
cpropertysym:=tcpupropertysym;
cconstsym:=tcpuconstsym;
cenumsym:=tcpuenumsym;
csyssym:=tcpusyssym;
end.

248
compiler/vis/aasmcpu.pas
View File

@ -1,248 +0,0 @@
{
Copyright (c) 1998-2001 by Florian Klaempfl and Pierre Muller
virtual instruction set family assembler instructions
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit aasmcpu;
{$i fpcdefs.inc}
interface
uses
cclasses,aasmtai,aasmdata,
aasmbase,globals,verbose,
cpubase,cpuinfo;
type
taicpu = class(taicpu_abstract)
opsize : topsize;
constructor op_none(op : tasmop;_size : topsize);
constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
constructor op_const(op : tasmop;_size : topsize;_op1 : longint);
constructor op_ref(op : tasmop;_size : topsize;_op1 : treference);
constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;_op2 : treference);
constructor op_ref_reg(op : tasmop;_size : topsize;_op1 : treference;_op2 : tregister);
constructor op_const_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister);
constructor op_const_ref(op : tasmop;_size : topsize;_op1 : longint;_op2 : treference);
{ this is for Jmp instructions }
constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
{ for DBxx opcodes }
constructor op_reg_sym(op: tasmop; _size : topsize; _op1: tregister; _op2 :tasmsymbol);
constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
private
procedure init(_size : topsize); { this need to be called by all constructor }
end;
tai_align = class(tai_align_abstract)
{ nothing to add }
end;
procedure InitAsm;
procedure DoneAsm;
implementation
{*****************************************************************************
Taicpu Constructors
*****************************************************************************}
procedure taicpu.init(_size : topsize);
begin
typ:=ait_instruction;
is_jmp:=false;
opsize:=_size;
ops:=0;
end;
constructor taicpu.op_none(op : tasmop;_size : topsize);
begin
inherited create(op);;
init(_size);
end;
constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
begin
inherited create(op);;
init(_size);
ops:=1;
loadreg(0,_op1);
end;
constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : longint);
begin
inherited create(op);;
init(_size);
ops:=1;
loadconst(0,aword(_op1));
end;
constructor taicpu.op_ref(op : tasmop;_size : topsize;_op1 : treference);
begin
inherited create(op);;
init(_size);
ops:=1;
loadref(0,_op1);
end;
constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
begin
inherited create(op);;
init(_size);
ops:=2;
loadreg(0,_op1);
loadreg(1,_op2);
end;
constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;_op2 : treference);
begin
inherited create(op);;
init(_size);
ops:=2;
loadreg(0,_op1);
loadref(1,_op2);
end;
constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister);
begin
inherited create(op);;
init(_size);
ops:=2;
loadconst(0,aword(_op1));
loadreg(1,_op2);
end;
constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : longint;_op2 : treference);
begin
inherited create(op);;
init(_size);
ops:=2;
loadconst(0,aword(_op1));
loadref(1,_op2);
end;
constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;_op1 : treference;_op2 : tregister);
begin
inherited create(op);;
init(_size);
ops:=2;
loadref(0,_op1);
loadreg(1,_op2);
end;
constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
begin
inherited create(op);;
init(_size);
ops:=1;
loadsymbol(0,_op1,0);
end;
constructor taicpu.op_reg_sym(op: tasmop; _size : topsize; _op1: tregister; _op2 :tasmsymbol);
begin
inherited create(op);
init(_size);
ops:=2;
loadreg(0,_op1);
loadsymbol(1,_op2,0);
end;
constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
begin
inherited create(op);
init(_size);
ops:=2;
loadsymbol(0,_op1,_op1ofs);
loadref(1,_op2);
end;
constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
begin
inherited create(op);
init(_size);
ops:=1;
loadsymbol(0,_op1,_op1ofs);
end;
constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
begin
inherited create(op);;
init(_size);
ops:=2;
loadreg(0,_op2);
loadsymbol(1,_op1,_op1ofs);
end;
constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
begin
inherited create(op);
init(_size);
condition:=cond;
ops:=1;
loadsymbol(0,_op1,0);
end;
procedure InitAsm;
begin
end;
procedure DoneAsm;
begin
end;
end.

609
compiler/vis/cpubase.pas
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@ -1,609 +0,0 @@
{
Copyright (c) 1998-2002 by the Free Pascal dev. team
Contains the base types for the virtual instruction set
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{ This Unit contains the base types for the Virtual Instruction machine
}
unit cpubase;
{$i fpcdefs.inc}
interface
uses
strings,cutils,cclasses,aasmbase,cpuinfo,cginfo;
{*****************************************************************************
Assembler Opcodes
*****************************************************************************}
type
TAsmOp=(a_none,a_beqs,a_bges,a_bgts,a_bles,a_blts,a_bnes,
a_bras,a_rets,a_bccs,a_bcss,a_bvcs,a_bvss,a_bbss,
a_bass,a_bats,a_bbts,a_beql,a_bgel,a_bgtl,a_blel,
a_bltl,a_bnel,a_bral,a_bsrl,a_bbsl,a_basl,a_batl,
a_bbtl,a_add,a_addc,a_and,a_asr,a_lsl,a_lsr,a_cmp,
a_sub,a_subb,a_divs,a_divu,a_mod,a_move,a_muls,a_mulu,
a_neg,a_not,a_or,a_xor,a_fadd,a_fcmp,a_fdiv,a_fmove,
a_fmul,a_fneg,a_fsub,a_fldd,a_flds,a_lbzx,a_lbsx,a_llsx,
a_llzx,a_lwsx,a_lwzx,a_fstd,a_fsts,a_stb,a_stl,a_stw,
a_syscall,a_nop,a_lims,a_orhi,a_lilo,a_call,a_popl,
a_pushl,
{ these are simplified mnemonics }
a_lea,a_limm,a_bxx
);
{# This should define the array of instructions as string }
op2strtable=array[tasmop] of string[8];
Const
{# First value of opcode enumeration }
firstop = low(tasmop);
{# Last value of opcode enumeration }
lastop = high(tasmop);
{*****************************************************************************
Registers
*****************************************************************************}
type
toldregister = (R_NO,R_R0,R_R1,R_R2,R_R3,
R_R4,R_R5,R_R6,R_R7,
R_R8,R_R9,R_R10,R_R11,
R_CCR,R_SP,R_FP,R_PC,
R_FP0,R_FP1,R_FP2,R_FP3,
R_FP4,R_FP5,R_FP6,R_FP7,
R_FP8,R_FP9,R_FP10,R_FP11,
R_FP12,R_FP13,R_FP14,R_FP15,
R_INTREGISTER,R_FPUREGISTER
);
{# Set type definition for registers }
tregisterset = set of Toldregister;
Tnewregister=word;
tregister=record
enum:toldregister;
number:Tnewregister;
end;
{ A type to store register locations for 64 Bit values. }
tregister64 = packed record
reglo,reghi : tregister;
end;
Tsuperregister=byte;
Tsubregister=byte;
Tsupregset=set of Tsuperregister;
{ alias for compact code }
treg64 = tregister64;
{# Type definition for the array of string of register nnames }
treg2strtable = array[toldregister] of string[5];
Const
{Special registers:}
NR_NO = $0000; {Invalid register}
{Normal registers:}
{General purpose registers:}
NR_R0 = $0100; NR_R1 = $0200; NR_R2 = $0300;
NR_R3 = $0400; NR_R4 = $0500; NR_R5 = $0600;
NR_R6 = $0700; NR_R7 = $0800; NR_R8 = $0900;
NR_R9 = $0A00; NR_R10 = $0B00; NR_R11 = $0C00;
NR_SP = $0D00; NR_FP = $0E00;
{Super registers:}
RS_R0 = $01; RS_R1 = $02; RS_R2 = $03;
RS_R3 = $04; RS_R4 = $05; RS_R5 = $06;
RS_R6 = $07; RS_R7 = $08; RS_R8 = $09;
RS_R9 = $0A; RS_R10 = $0B; RS_R11 = $0C;
RS_SP = $0D; RS_FP = $0E;
{Subregisters:}
R_SUBL = $00;
R_SUBW = $01;
R_SUBD = $02;
{# First register in the tregister enumeration }
firstreg = low(toldregister);
{# Last register in the tregister enumeration }
lastreg = high(toldregister);
first_supreg = $01;
last_supreg = $0c;
std_reg2str : treg2strtable = ('',
'r0','r1','r2','r3','r4','r5','r6','r7','r8','r9','r10','r11','ccr',
'sp','fp','pc','fp0','fp1','fp2','fp3','fp4','fp5','fp6','fp7',
'fp8','fp9','fp10','fp11','fp12','fp13','fp14','fp15','',''
);
{*****************************************************************************
Conditions
*****************************************************************************}
type
TAsmCond=(C_None,
C_EQ, { equal }
C_NE, { not equal }
C_GE, { greater or equal (signed) }
C_GT, { greater than (signed) }
C_LE, { less or equal (signed) }
C_LT, { less than (signed) }
C_LS, { lower or same (unordered) }
C_AS, { above or same (unordered) }
C_AT, { above than (unordered) }
C_BT, { below than (unordered) }
C_CC, { carry clear }
C_CS { carry set }
);
const
cond2str:array[TAsmCond] of string[3]=('',
'eq','ne','ge','gt','le','lt','ls','as',
'at','bt','cc','cs');
{*****************************************************************************
Flags
*****************************************************************************}
type
TResFlags = (
F_E, { zero flag = equal }
F_NE, { !zero_flag = not equal }
F_G, { greater (signed) }
F_L, { less (signed) }
F_GE,
F_LE,
F_C, { carry flag }
F_NC, { !carry flag }
F_A, { greater (unsigned) }
F_AE,
F_B, { less (unsigned) }
F_BE
);
{*****************************************************************************
Reference
*****************************************************************************}
type
trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
{ reference record }
preference = ^treference;
treference = packed record
base,
index : tregister;
offset : longint;
symbol : tasmsymbol;
offsetfixup : longint;
options : trefoptions;
alignment : byte;
end;
{ reference record }
pparareference = ^tparareference;
tparareference = packed record
index : tregister;
offset : aword;
end;
{*****************************************************************************
Operand
*****************************************************************************}
type
toptype=(top_none,top_reg,top_ref,top_const,top_symbol,top_bool);
toper=record
ot : longint;
case typ : toptype of
top_none : ();
top_reg : (reg:tregister);
top_ref : (ref:^treference);
top_const : (val:aword);
top_symbol : (sym:tasmsymbol;symofs:longint);
top_bool : (b: boolean);
end;
{*****************************************************************************
Operand Sizes
*****************************************************************************}
{ S_NO = No Size of operand }
{ S_B = 8-bit size operand }
{ S_W = 16-bit size operand }
{ S_L = 32-bit size operand }
{ Floating point types }
{ S_FS = single type (32 bit) }
{ S_FD = double/64bit integer }
{ S_FX = Extended type }
topsize = (S_NO,S_B,S_W,S_L,S_FS,S_FD,S_FX,S_IQ);
{*****************************************************************************
Generic Location
*****************************************************************************}
type
TLoc=(
{ added for tracking problems}
LOC_INVALID,
{ ordinal constant }
LOC_CONSTANT,
{ in a processor register }
LOC_REGISTER,
{ Constant register which shouldn't be modified }
LOC_CREGISTER,
{ FPU register}
LOC_FPUREGISTER,
{ Constant FPU register which shouldn't be modified }
LOC_CFPUREGISTER,
{ multimedia register }
LOC_MMREGISTER,
{ Constant multimedia reg which shouldn't be modified }
LOC_CMMREGISTER,
{ in memory }
LOC_REFERENCE,
{ in memory (constant) }
LOC_CREFERENCE,
{ boolean results only, jump to false or true label }
LOC_JUMP,
{ boolean results only, flags are set }
LOC_FLAGS
);
{ tparamlocation describes where a parameter for a procedure is stored.
References are given from the caller's point of view. The usual
TLocation isn't used, because contains a lot of unnessary fields.
}
tparalocation = packed record
size : TCGSize;
{ The location type where the parameter is passed, usually
LOC_REFERENCE,LOC_REGISTER or LOC_FPUREGISTER
}
loc : TLoc;
{ The stack pointer must be decreased by this value before
the parameter is copied to the given destination.
This allows to "encode" pushes with tparalocation.
On the PowerPC, this field is unsed but it is there
because several generic code accesses it.
}
sp_fixup : longint;
case TLoc of
LOC_REFERENCE : (reference : tparareference);
LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
LOC_REGISTER,LOC_CREGISTER : (
case longint of
1 : (register,register64.reghi : tregister);
{ overlay a register64.reglo }
2 : (register64.reglo : tregister);
{ overlay a 64 Bit register type }
3 : (reg64 : tregister64);
4 : (register64 : tregister64);
);
end;
treglocation = packed record
case longint of
1 : (register,register64.reghi : tregister);
{ overlay a register64.reglo }
2 : (register64.reglo : tregister);
{ overlay a 64 Bit register type }
3 : (reg64 : tregister64);
4 : (register64 : tregister64);
end;
tlocation = packed record
size : TCGSize;
loc : tloc;
case tloc of
LOC_CREFERENCE,LOC_REFERENCE : (reference : treference);
LOC_CONSTANT : (
case longint of
1 : (value : AWord);
{ can't do this, this layout depends on the host cpu. Use }
{ lo(valueqword)/hi(valueqword) instead (JM) }
{ 2 : (valuelow, valuehigh:AWord); }
{ overlay a complete 64 Bit value }
3 : (valueqword : qword);
);
LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
LOC_REGISTER,LOC_CREGISTER : (
case longint of
1 : (register64.reglo,register64.reghi : tregister);
2 : (register : tregister);
{ overlay a 64 Bit register type }
3 : (reg64 : tregister64);
4 : (register64 : tregister64);
);
LOC_FLAGS : (resflags : tresflags);
end;
{*****************************************************************************
Constants
*****************************************************************************}
const
max_operands = 2;
lvaluelocations = [LOC_REFERENCE, LOC_CREGISTER, LOC_CFPUREGISTER,
LOC_CMMREGISTER];
{# Constant defining possibly all registers which might require saving }
ALL_REGISTERS = [R_FP0..R_FP15];
general_registers = [R_R0..R_R11];
{# low and high of the available maximum width integer general purpose }
{ registers }
LoGPReg = R_R0;
HiGPReg = R_R11;
{# low and high of every possible width general purpose register (same as }
{ above on most architctures apart from the 80x86) }
LoReg = R_R0;
HiReg = R_R11;
maxintregs = 12;
maxfpuregs = 16;
maxaddrregs = 0;
maxvarregs = 10;
varregs : Array [1..maxvarregs] of toldregister =
(R_R2,R_R3,R_R4,R_R5,R_R6,R_R7,R_R8,R_R9,R_R10,R_R11);
maxfpuvarregs = 15;
fpuvarregs : Array [1..maxfpuvarregs] of toldregister =
(R_FP1,R_FP2,R_FP3,
R_FP4,R_FP5,R_FP6,
R_FP7,R_FP8,R_FP9,
R_FP10,R_FP11,R_FP12,
R_FP13,R_FP14,R_FP15);
max_param_regs_int = 0;
max_param_regs_fpu = 0;
max_param_regs_mm = 0;
{# Registers which are defined as scratch and no need to save across
routine calls or in assembler blocks.
}
max_scratch_regs = 2;
scratch_regs: Array[1..max_scratch_regs] of Tsuperregister = (RS_R0,RS_R1);
{*****************************************************************************
Default generic sizes
*****************************************************************************}
{# Defines the default address size for a processor, }
OS_ADDR = OS_32;
{# the natural int size for a processor,
has to match osuinttype/ossinttype as initialized in psystem }
OS_INT = OS_32;
{# the maximum float size for a processor, }
OS_FLOAT = OS_F64;
{# the size of a vector register for a processor }
OS_VECTOR = OS_NO;
{*****************************************************************************
GDB Information
*****************************************************************************}
{# Register indexes for stabs information, when some
parameters or variables are stored in registers.
Currently unsupported by abstract machine
}
stab_regindex : array[toldregister] of shortint =
(-1,
{ r0..r11 }
-1,-1,-1,-1,-1,-1,
-1,-1,-1,-1,-1,-1,
{ sp,fp,ccr,pc }
-1,-1,-1,-1,
{ FP0..FP7 }
-1,-1,-1,-1,-1,-1,-1,-1,
{ FP8..FP15 }
-1,-1,-1,-1,-1,-1,-1,-1,
{ invalid }
-1,-1
);
{*****************************************************************************
Generic Register names
*****************************************************************************}
{# Stack pointer register }
stack_pointer_reg = R_SP;
NR_STACK_POINTER_REG = NR_SP;
RS_STACK_POINTER_REG = RS_SP;
{# Frame pointer register }
frame_pointer_reg = R_FP;
NR_FRAME_POINTER_REG = NR_FP;
RS_FRAME_POINTER_REG = RS_FP;
{# Self pointer register : contains the instance address of an
object or class. }
self_pointer_reg = R_R11;
NR_SELF_POINTER_REG = NR_R11;
RS_SELF_POINTER_REG = RS_R11;
{# Register for addressing absolute data in a position independant way,
such as in PIC code. The exact meaning is ABI specific.
}
pic_offset_reg = R_R10;
{# Results are returned in this register (32-bit values) }
accumulator = R_R0;
NR_ACCUMULATOR = NR_R0;
RS_ACCUMULATOR = RS_R0;
{the return_result_reg, is used inside the called function to store its return
value when that is a scalar value otherwise a pointer to the address of the
result is placed inside it}
return_result_reg = accumulator;
{the function_result_reg contains the function result after a call to a scalar
function othewise it contains a pointer to the returned result}
function_result_reg = accumulator;
{# Hi-Results are returned in this register (64-bit value high register) }
accumulatorhigh = R_R1;
NR_ACCUMULATORHIGH = NR_R1;
RS_ACCUMULATORHIGH = RS_R1;
fpu_result_reg = R_FP0;
mmresultreg = R_NO;
{*****************************************************************************
GCC /ABI linking information
*****************************************************************************}
{# Registers which must be saved when calling a routine declared as
cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
saved should be the ones as defined in the target ABI and / or GCC.
This value can be deduced from CALLED_USED_REGISTERS array in the
GCC source.
}
std_saved_registers = [RS_R0,RS_R1,RS_R10,RS_R11];
{# Required parameter alignment when calling a routine declared as
stdcall and cdecl. The alignment value should be the one defined
by GCC or the target ABI.
The value of this constant is equal to the constant
PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
}
std_param_align = 4; { for 32-bit version only }
{*****************************************************************************
Helpers
*****************************************************************************}
function is_calljmp(o:tasmop):boolean;
procedure inverse_flags(var r : TResFlags);
function flags_to_cond(const f: TResFlags) : TAsmCond;
procedure convert_register_to_enum(var r:Tregister);
function cgsize2subreg(s:Tcgsize):Tsubregister;
implementation
uses
verbose;
{*****************************************************************************
Helpers
*****************************************************************************}
function is_calljmp(o:tasmop):boolean;
begin
is_calljmp := false;
if o in [a_bxx,a_call,a_beqs..a_bbtl] then
is_calljmp := true;
end;
procedure inverse_flags(var r: TResFlags);
const flagsinvers : array[F_E..F_BE] of tresflags =
(F_NE,F_E,
F_LE,F_GE,
F_L,F_G,
F_NC,F_C,
F_BE,F_B,
F_AE,F_A);
begin
r:=flagsinvers[r];
end;
function flags_to_cond(const f: TResFlags) : TAsmCond;
const flags2cond : array[tresflags] of tasmcond =
(
{F_E} C_EQ,
{F_NE} C_NE,
{F_G } C_GT,
{F_L } C_LT,
{F_GE} C_GE,
{F_LE} C_LE,
{F_C} C_CS,
{F_NC} C_CC,
{F_A} C_AT,
{F_AE} C_AS,
{F_B} C_BT,
{F_BE} C_LS);
begin
flags_to_cond := flags2cond[f];
end;
procedure convert_register_to_enum(var r:Tregister);
begin
if r.enum = R_INTREGISTER then
case r.number of
NR_NO: r.enum:= R_NO;
NR_R0: r.enum:= R_R0;
NR_R1: r.enum:= R_R1;
NR_R2: r.enum:= R_R2;
NR_R3: r.enum:= R_R3;
NR_R4: r.enum:= R_R4;
NR_R5: r.enum:= R_R5;
NR_R6: r.enum:= R_R6;
NR_R7: r.enum:= R_R7;
NR_R8: r.enum:= R_R8;
NR_R9: r.enum:= R_R9;
NR_R10: r.enum:= R_R10;
NR_R11: r.enum:= R_R11;
else
internalerror(200301082);
end;
end;
function cgsize2subreg(s:Tcgsize):Tsubregister;
begin
case s of
OS_8,OS_S8:
cgsize2subreg:=R_SUBL;
OS_16,OS_S16:
cgsize2subreg:=R_SUBW;
OS_32,OS_S32:
cgsize2subreg:=R_SUBD;
else
internalerror(200301231);
end;
end;
end.

79
compiler/vis/cpuinfo.pas
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@ -1,79 +0,0 @@
{
Copyright (c) 1998-2002 by the Free Pascal development team
Basic Processor information for the virtual instruction set
See the file COPYING.FPC, included in this distribution,
for details about the copyright.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
**********************************************************************}
Unit CPUInfo;
Interface
uses
globtype;
Type
{ Architecture word - Native unsigned type }
AWord = Longword;
PAWord = ^AWord;
{ this must be an ordinal type with the same size as a pointer }
{ to allow some dirty type casts for example when using }
{ tconstsym.value }
{ Note: must be unsigned!! Otherwise, ugly code like }
{ pointer(-1) will result in a pointer with the value }
{ $fffffffffffffff on a 32bit machine if the compiler uses }
{ int64 constants internally (JM) }
TConstPtrUInt = Longword;
bestreal = double;
{$if FPC_FULLVERSION>20700}
bestrealrec = TDoubleRec;
{$endif FPC_FULLVERSION>20700}
ts32real = single;
ts64real = double;
ts80real = extended;
ts64comp = comp;
pbestreal=^bestreal;
{ possible supported processors for this target }
tcputype = (cpu_none);
tcontrollertype =
(ct_none
);
Const
{ Is there support for dealing with multiple microcontrollers available }
{ for this platform? }
ControllerSupport = false;
{# Size of native extended floating point type }
extended_size = 8;
{# Size of a pointer }
sizeof(aint) = 4;
{# Size of a multimedia register }
mmreg_size = 8;
{ target cpu string (used by compiler options) }
target_cpu_string = 'vis';
{ We know that there are fields after sramsize
but we don't care about this warning }
{$PUSH}
{$WARN 3177 OFF}
embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
(
(controllertypestr:''; controllerunitstr:''; flashbase:0; flashsize:0; srambase:0; sramsize:0));
{$POP}
Implementation
end.

49
compiler/vis/cpunode.pas
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@ -1,49 +0,0 @@
{
Copyright (c) 2000-2002 by Florian Klaempfl
Includes the Virtual instrution set code generator
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit cpunode;
{$i fpcdefs.inc}
interface
implementation
uses
{ generic nodes }
ncgbas,ncgld,ncgflw,ncgcnv,ncgmem,ncgcon,ncgcal,ncgset,ncginl,
{ to be able to only parts of the generic code,
the processor specific nodes must be included
after the generic one (FK)
}
// nvisadd,
// nviscal,
// nviscon,
// nvisflw,
// nvismem,
// nvisinl,
// nvismat,
// nviscnv,
{ symtable }
symcpu
;
end.

69
compiler/vis/cpupara.pas
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@ -1,69 +0,0 @@
{
Copyright (c) 2002 by Florian Klaempfl
Generates the argument location information for the
virtual instruction set machine
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
{ Generates the argument location information for 680x0.
}
unit cpupara;
{$i fpcdefs.inc}
interface
uses
cpubase,
symdef,paramgr;
type
{ Returns the location for the nr-st 32 Bit int parameter
if every parameter before is an 32 Bit int parameter as well
and if the calling conventions for the helper routines of the
rtl are used.
}
tcpuparamanager = class(tparamanager)
procedure create_param_loc_info(p : tabstractprocdef);override;
function getselflocation(p : tabstractprocdef) : tparalocation;override;
end;
implementation
uses
verbose,
globals,
globtype,
systems,
cpuinfo,cginfo,cgbase,
defutil;
procedure tcpuparamanager.create_param_loc_info(p : tabstractprocdef);
var
param_offset : integer;
hp : tparaitem;
begin
end;
function tcpuparamanager.getselflocation(p : tabstractprocdef) : tparalocation;
begin
end;
begin
paramanager:=tcpuparamanager.create;
end.