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https://gitlab.com/freepascal.org/fpc/source.git
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o slightly modified patch by John Clymer:
* converts the embedded information into controller specific records (arm and avr) * new cpu-specific units for several Stellaris (Fury and Tempest class) targets, + STM32F103RB - old Stellaris unit has been removed git-svn-id: trunk@18848 -
This commit is contained in:
florian
parent
e5c796e9fd
commit
a08dfdf803
3
.gitattributes
vendored
3
.gitattributes
vendored
@ -7009,8 +7009,9 @@ rtl/darwin/x86_64/sighnd.inc svneol=native#text/plain
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rtl/embedded/Makefile svneol=native#text/plain
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rtl/embedded/Makefile.fpc svneol=native#text/plain
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rtl/embedded/arm/at91sam7x256.pp svneol=native#text/plain
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rtl/embedded/arm/lm3fury.pp svneol=native#text/pascal
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rtl/embedded/arm/lm3tempest.pp svneol=native#text/pascal
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rtl/embedded/arm/lpc21x4.pp svneol=native#text/plain
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rtl/embedded/arm/stellaris.pp svneol=native#text/plain
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rtl/embedded/arm/stm32f103.pp svneol=native#text/plain
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rtl/embedded/avr/atmega128.pp svneol=native#text/plain
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rtl/embedded/avr/start.inc svneol=native#text/plain
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@ -73,12 +73,89 @@ Type
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ct_at91sam7xc256,
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{ STMicroelectronics }
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ct_stm32f103rb,
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ct_stm32f103re,
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{ TI }
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ct_stellaris
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{ TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
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ct_lm3s1110,
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ct_lm3s1133,
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ct_lm3s1138,
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ct_lm3s1150,
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ct_lm3s1162,
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ct_lm3s1165,
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ct_lm3s1166,
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ct_lm3s2110,
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ct_lm3s2139,
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ct_lm3s6100,
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ct_lm3s6110,
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{ TI - Fury Class - 128K Flash, 32K SRAM devices }
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ct_lm3s1601,
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ct_lm3s1608,
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ct_lm3s1620,
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ct_lm3s1635,
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ct_lm3s1636,
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ct_lm3s1637,
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ct_lm3s1651,
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ct_lm3s2601,
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ct_lm3s2608,
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ct_lm3s2620,
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ct_lm3s2637,
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ct_lm3s2651,
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ct_lm3s6610,
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ct_lm3s6611,
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ct_lm3s6618,
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ct_lm3s6633,
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ct_lm3s6637,
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ct_lm3s8630,
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{ TI - Fury Class - 256K Flash, 64K SRAM devices }
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ct_lm3s1911,
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ct_lm3s1918,
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ct_lm3s1937,
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ct_lm3s1958,
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ct_lm3s1960,
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ct_lm3s1968,
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ct_lm3s1969,
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ct_lm3s2911,
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ct_lm3s2918,
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ct_lm3s2919,
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ct_lm3s2939,
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ct_lm3s2948,
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ct_lm3s2950,
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ct_lm3s2965,
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ct_lm3s6911,
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ct_lm3s6918,
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ct_lm3s6938,
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ct_lm3s6950,
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ct_lm3s6952,
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ct_lm3s6965,
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ct_lm3s8930,
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ct_lm3s8933,
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ct_lm3s8938,
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ct_lm3s8962,
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ct_lm3s8970,
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ct_lm3s8971,
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{ TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
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ct_lm3s5951,
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ct_lm3s5956,
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ct_lm3s1b21,
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ct_lm3s2b93,
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ct_lm3s5b91,
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ct_lm3s9b81,
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ct_lm3s9b90,
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ct_lm3s9b92,
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ct_lm3s9b95,
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ct_lm3s9b96,
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// generic Thumb2 target
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ct_thumb2bare
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);
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{$I controllerunit.inc}
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Const
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{# Size of native extended floating point type }
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extended_size = 12;
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@ -125,44 +202,777 @@ Const
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'VFPV3'
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);
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controllertypestr : array[tcontrollertype] of string[20] =
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('',
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'LPC2114',
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'LPC2124',
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'LPC2194',
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'AT91SAM7S256',
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'AT91SAM7SE256',
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'AT91SAM7X256',
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'AT91SAM7XC256',
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'STM32F103RE',
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'STELLARIS'
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);
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controllerunitstr : array[tcontrollertype] of string[20] =
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('',
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'LPC21x4',
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'LPC21x4',
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'LPC21x4',
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'AT91SAM7x256',
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'AT91SAM7x256',
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'AT91SAM7x256',
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'AT91SAM7x256',
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'STM32F103',
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'STELLARIS'
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);
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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((
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controllertypestr:'';
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controllerunitstr:'';
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interruptvectors:0;
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flashbase:0;
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flashsize:0;
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srambase:0;
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sramsize:0
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),
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interruptvectors : array[tcontrollertype] of longint =
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(0,
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8,
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8,
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8,
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8,
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8,
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8,
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8,
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12+59, { XL-density }
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12 { No model specified }
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);
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(
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controllertypestr:'LPC2114';
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controllerunitstr:'LPC21x4';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$40000000;
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sramsize:$00004000
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),
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(
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controllertypestr:'LPC2124';
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controllerunitstr:'LPC21x4';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$40000000;
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sramsize:$00004000
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),
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(
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controllertypestr:'LPC2194';
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controllerunitstr:'LPC21x4';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$40000000;
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sramsize:$00004000
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),
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(
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controllertypestr:'AT91SAM7S256';
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controllerunitstr:'AT91SAM7x256';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$00200000;
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sramsize:$00010000
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),
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(
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controllertypestr:'AT91SAM7SE256';
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controllerunitstr:'AT91SAM7x256';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$00200000;
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sramsize:$00010000
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),
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(
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controllertypestr:'AT91SAM7X256';
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controllerunitstr:'AT91SAM7x256';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$00200000;
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sramsize:$00010000
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),
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(
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controllertypestr:'AT91SAM7XC256';
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controllerunitstr:'AT91SAM7x256';
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interruptvectors:8;
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flashbase:$00000000;
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flashsize:$00040000;
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srambase:$00200000;
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sramsize:$00010000
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),
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// ct_stm32f103rb,
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(
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controllertypestr:'STM32F103RB';
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controllerunitstr:'STM32F103';
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interruptvectors:12;
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flashbase:$08000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00005000
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),
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// ct_stm32f103re,
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(
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controllertypestr:'STM32F103RE';
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controllerunitstr:'STM32F103';
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interruptvectors:12;
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flashbase:$08000000;
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flashsize:$00080000;
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srambase:$20000000;
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sramsize:$00010000
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),
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{ TI - 64 K Flash, 16 K SRAM Devices }
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// ct_lm3s1110,
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(
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controllertypestr:'LM3S1110';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1133,
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(
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controllertypestr:'LM3S1133';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1138,
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(
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controllertypestr:'LM3S1138';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1150,
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(
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controllertypestr:'LM3S1150';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1162,
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(
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controllertypestr:'LM3S1162';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1165,
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(
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controllertypestr:'LM3S1165';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s1166,
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(
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controllertypestr:'LM3S1166';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s2110,
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(
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controllertypestr:'LM3S2110';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s2139,
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(
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controllertypestr:'LM3S2139';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s6100,
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(
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controllertypestr:'LM3S6100';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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// ct_lm3s6110,
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(
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controllertypestr:'LM3S6110';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00010000;
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srambase:$20000000;
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sramsize:$00004000
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),
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{ TI - 128K Flash, 32K SRAM devices }
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// ct_lm3s1601,
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(
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controllertypestr:'LM3S1601';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00008000
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),
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// ct_lm3s1608,
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(
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controllertypestr:'LM3S1608';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00008000
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),
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// ct_lm3s1620,
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(
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controllertypestr:'LM3S1620';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00008000
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),
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// ct_lm3s1635,
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(
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controllertypestr:'LM3S1635';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00008000
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),
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// ct_lm3s1636,
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(
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controllertypestr:'LM3S1636';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
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sramsize:$00008000
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),
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// ct_lm3s1637,
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(
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controllertypestr:'LM3S1637';
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controllerunitstr:'LM3FURY';
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interruptvectors:72;
|
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flashbase:$00000000;
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flashsize:$00020000;
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srambase:$20000000;
|
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sramsize:$00008000
|
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),
|
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// ct_lm3s1651,
|
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(
|
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controllertypestr:'LM3S1651';
|
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controllerunitstr:'LM3FURY';
|
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interruptvectors:72;
|
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flashbase:$00000000;
|
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flashsize:$00020000;
|
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srambase:$20000000;
|
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sramsize:$00008000
|
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),
|
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// ct_lm3s2601,
|
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(
|
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controllertypestr:'LM3S2601';
|
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controllerunitstr:'LM3FURY';
|
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interruptvectors:72;
|
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flashbase:$00000000;
|
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flashsize:$00020000;
|
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srambase:$20000000;
|
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sramsize:$00008000
|
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),
|
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// ct_lm3s2608,
|
||||
(
|
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controllertypestr:'LM3S2608';
|
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controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
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flashsize:$00020000;
|
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srambase:$20000000;
|
||||
sramsize:$00008000
|
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),
|
||||
// ct_lm3s2620,
|
||||
(
|
||||
controllertypestr:'LM3S2620';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
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flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s2637,
|
||||
(
|
||||
controllertypestr:'LM3S2637';
|
||||
controllerunitstr:'LM3FURY';
|
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interruptvectors:72;
|
||||
flashbase:$00000000;
|
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flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s2651,
|
||||
(
|
||||
controllertypestr:'LM3S2651';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
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flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s6610,
|
||||
(
|
||||
controllertypestr:'LM3S6610';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s6611,
|
||||
(
|
||||
controllertypestr:'LM3S6611';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s6618,
|
||||
(
|
||||
controllertypestr:'LM3S6618';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s6633,
|
||||
(
|
||||
controllertypestr:'LM3S6633';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s6637,
|
||||
(
|
||||
controllertypestr:'LM3S6637';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
// ct_lm3s8630,
|
||||
(
|
||||
controllertypestr:'LM3S8630';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00020000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00008000
|
||||
),
|
||||
|
||||
{ TI - 256K Flash, 64K SRAM devices }
|
||||
// ct_lm3s1911,
|
||||
(
|
||||
controllertypestr:'LM3S1911';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1918,
|
||||
(
|
||||
controllertypestr:'LM3S1918';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1937,
|
||||
(
|
||||
controllertypestr:'LM3S1937';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1958,
|
||||
(
|
||||
controllertypestr:'LM3S1958';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1960,
|
||||
(
|
||||
controllertypestr:'LM3S1960';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1968,
|
||||
(
|
||||
controllertypestr:'LM3S1968';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1969,
|
||||
(
|
||||
controllertypestr:'LM3S1969';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2911,
|
||||
(
|
||||
controllertypestr:'LM3S2911';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2918,
|
||||
(
|
||||
controllertypestr:'LM3S2918';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2919,
|
||||
(
|
||||
controllertypestr:'LM3S2919';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2939,
|
||||
(
|
||||
controllertypestr:'LM3S2939';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2948,
|
||||
(
|
||||
controllertypestr:'LM3S2948';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2950,
|
||||
(
|
||||
controllertypestr:'LM3S2950';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2965,
|
||||
(
|
||||
controllertypestr:'LM3S2965';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6911,
|
||||
(
|
||||
controllertypestr:'LM3S6911';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6918,
|
||||
(
|
||||
controllertypestr:'LM3S6918';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6938,
|
||||
(
|
||||
controllertypestr:'LM3S6938';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6950,
|
||||
(
|
||||
controllertypestr:'LM3S6950';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6952,
|
||||
(
|
||||
controllertypestr:'LM3S6952';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s6965,
|
||||
(
|
||||
controllertypestr:'LM3S6965';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8930,
|
||||
(
|
||||
controllertypestr:'LM3S8930';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8933,
|
||||
(
|
||||
controllertypestr:'LM3S8933';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8938,
|
||||
(
|
||||
controllertypestr:'LM3S8938';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8962,
|
||||
(
|
||||
controllertypestr:'LM3S8962';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8970,
|
||||
(
|
||||
controllertypestr:'LM3S8970';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s8971,
|
||||
(
|
||||
controllertypestr:'LM3S8971';
|
||||
controllerunitstr:'LM3FURY';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
|
||||
{ TI - Tempest parts - 256 K Flash, 64 K SRAM }
|
||||
// ct_lm3s5951,
|
||||
(
|
||||
controllertypestr:'LM3S5951';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s5956,
|
||||
(
|
||||
controllertypestr:'LM3S5956';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s1b21,
|
||||
(
|
||||
controllertypestr:'LM3S1B21';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s2b93,
|
||||
(
|
||||
controllertypestr:'LM3S2B93';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s5b91,
|
||||
(
|
||||
controllertypestr:'LM3S5B91';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s9b81,
|
||||
(
|
||||
controllertypestr:'LM3S9B81';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s9b90,
|
||||
(
|
||||
controllertypestr:'LM3S9B90';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s9b92,
|
||||
(
|
||||
controllertypestr:'LM3S9B92';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s9b95,
|
||||
(
|
||||
controllertypestr:'LM3S9B95';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// ct_lm3s9b96,
|
||||
(
|
||||
controllertypestr:'LM3S9B96';
|
||||
controllerunitstr:'LM3TEMPEST';
|
||||
interruptvectors:72;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00040000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00010000
|
||||
),
|
||||
// bare bones Thumb2
|
||||
(
|
||||
controllertypestr:'THUMB2_BARE';
|
||||
controllerunitstr:'THUMB2_BARE';
|
||||
interruptvectors:128;
|
||||
flashbase:$00000000;
|
||||
flashsize:$00100000;
|
||||
srambase:$20000000;
|
||||
sramsize:$00100000
|
||||
)
|
||||
);
|
||||
|
||||
vfp_scalar = [fpu_vfpv2,fpu_vfpv3];
|
||||
|
||||
|
||||
@ -112,23 +112,75 @@ Const
|
||||
'LIBGCC'
|
||||
);
|
||||
|
||||
controllertypestr : array[tcontrollertype] of string[20] =
|
||||
('',
|
||||
'ATMEGA16',
|
||||
'ATMEGA32',
|
||||
'ATMEGA48',
|
||||
'ATMEGA64',
|
||||
'ATMEGA128'
|
||||
);
|
||||
embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
|
||||
((
|
||||
controllertypestr:'';
|
||||
controllerunitstr:'';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:0;
|
||||
srambase:0;
|
||||
sramsize:0;
|
||||
eeprombase:0;
|
||||
eepromsize:0
|
||||
),
|
||||
(
|
||||
controllertypestr:'ATMEGA16';
|
||||
controllerunitstr:'ATMEGA16';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:$4000;
|
||||
srambase:0;
|
||||
sramsize:1024;
|
||||
eeprombase:0;
|
||||
eepromsize:512
|
||||
),
|
||||
(
|
||||
controllertypestr:'ATMEGA32';
|
||||
controllerunitstr:'ATMEGA32';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:$8000;
|
||||
srambase:0;
|
||||
sramsize:1024;
|
||||
eeprombase:0;
|
||||
eepromsize:512
|
||||
),
|
||||
(
|
||||
controllertypestr:'ATMEGA48';
|
||||
controllerunitstr:'ATMEGA48';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:$1000;
|
||||
srambase:0;
|
||||
sramsize:512;
|
||||
eeprombase:0;
|
||||
eepromsize:256;
|
||||
),
|
||||
(
|
||||
controllertypestr:'ATMEGA64';
|
||||
controllerunitstr:'ATMEGA64';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:$10000;
|
||||
srambase:0;
|
||||
sramsize:4096;
|
||||
eeprombase:0;
|
||||
eepromsize:2048;
|
||||
),
|
||||
(
|
||||
controllertypestr:'ATMEGA128';
|
||||
controllerunitstr:'ATMEGA128';
|
||||
interruptvectors:0;
|
||||
flashbase:0;
|
||||
flashsize:$20000;
|
||||
srambase:0;
|
||||
sramsize:4096;
|
||||
eeprombase:0;
|
||||
eepromsize:4096;
|
||||
)
|
||||
);
|
||||
|
||||
controllerunitstr : array[tcontrollertype] of string[20] =
|
||||
('',
|
||||
'ATMEGA16',
|
||||
'ATMEGA32',
|
||||
'ATMEGA48',
|
||||
'ATMEGA64',
|
||||
'ATMEGA128'
|
||||
);
|
||||
{ Supported optimizations, only used for information }
|
||||
supported_optimizerswitches = genericlevel1optimizerswitches+
|
||||
genericlevel2optimizerswitches+
|
||||
|
||||
@ -1108,7 +1108,7 @@ implementation
|
||||
result:=false;
|
||||
hs:=Upper(s);
|
||||
for t:=low(tcontrollertype) to high(tcontrollertype) do
|
||||
if controllertypestr[t]=hs then
|
||||
if embedded_controllers[t].controllertypestr=hs then
|
||||
begin
|
||||
a:=t;
|
||||
result:=true;
|
||||
|
||||
@ -224,6 +224,13 @@ interface
|
||||
);
|
||||
twpoptimizerswitches = set of twpoptimizerswitch;
|
||||
|
||||
type
|
||||
{ Used by ARM / AVR to differentiate between specific microcontrollers }
|
||||
tcontrollerdatatype = record
|
||||
controllertypestr, controllerunitstr: string[20];
|
||||
interruptvectors:integer;
|
||||
flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize: dword;
|
||||
end;
|
||||
|
||||
const
|
||||
OptimizerSwitchStr : array[toptimizerswitch] of string[10] = ('',
|
||||
|
||||
@ -3153,7 +3153,7 @@ implementation
|
||||
function GetInterruptTableLength: longint;
|
||||
begin
|
||||
{$if defined(ARM)}
|
||||
result:=interruptvectors[current_settings.controllertype];
|
||||
result:=embedded_controllers[current_settings.controllertype].interruptvectors;
|
||||
{$else}
|
||||
result:=0;
|
||||
{$endif}
|
||||
|
||||
@ -286,7 +286,7 @@ begin
|
||||
}
|
||||
begin
|
||||
hs:=s;
|
||||
hs1:=ControllerTypeStr[controllertype];
|
||||
hs1:=embedded_controllers[controllertype].ControllerTypeStr;
|
||||
if hs1<>'' then
|
||||
begin
|
||||
Replace(hs,'$CONTROLLERTYPES',hs1);
|
||||
|
||||
@ -714,8 +714,9 @@ implementation
|
||||
|
||||
{ CPU targets with microcontroller support can add a controller specific unit }
|
||||
{$if defined(ARM) or defined(AVR)}
|
||||
if (target_info.system in systems_embedded) and (current_settings.controllertype<>ct_none) then
|
||||
AddUnit(controllerunitstr[current_settings.controllertype]);
|
||||
if (target_info.system in systems_embedded) and (current_settings.controllertype<>ct_none) and
|
||||
(embedded_controllers[current_settings.controllertype].controllerunitstr<>'') then
|
||||
AddUnit(embedded_controllers[current_settings.controllertype].controllerunitstr);
|
||||
{$endif ARM}
|
||||
end;
|
||||
|
||||
|
||||
@ -79,6 +79,7 @@ Var
|
||||
linklibc : boolean;
|
||||
found1,
|
||||
found2 : boolean;
|
||||
LinkStr : string;
|
||||
begin
|
||||
WriteResponseFile:=False;
|
||||
linklibc:=(SharedLibFiles.Find('c')<>nil);
|
||||
@ -216,49 +217,116 @@ begin
|
||||
|
||||
{$ifdef ARM}
|
||||
case current_settings.controllertype of
|
||||
ct_none:
|
||||
;
|
||||
ct_lpc2114,
|
||||
ct_lpc2124,
|
||||
ct_lpc2194:
|
||||
with linkres do
|
||||
begin
|
||||
Add('ENTRY(_START)');
|
||||
Add('MEMORY');
|
||||
Add('{');
|
||||
Add(' flash : ORIGIN = 0, LENGTH = 256K');
|
||||
Add(' ram : ORIGIN = 0x40000000, LENGTH = 16K');
|
||||
Add('}');
|
||||
Add('_stack_top = 0x40003FFC;');
|
||||
end;
|
||||
ct_none:
|
||||
begin
|
||||
end;
|
||||
ct_lpc2114,
|
||||
ct_lpc2124,
|
||||
ct_lpc2194,
|
||||
ct_at91sam7s256,
|
||||
ct_at91sam7se256,
|
||||
ct_at91sam7x256,
|
||||
ct_at91sam7xc256:
|
||||
with linkres do
|
||||
begin
|
||||
Add('ENTRY(_START)');
|
||||
Add('MEMORY');
|
||||
Add('{');
|
||||
Add(' flash : ORIGIN = 0, LENGTH = 256K');
|
||||
Add(' ram : ORIGIN = 0x200000, LENGTH = 64K');
|
||||
Add('}');
|
||||
Add('_stack_top = 0x20FFFC;');
|
||||
end;
|
||||
ct_stm32f103re:
|
||||
with linkres do
|
||||
begin
|
||||
Add('ENTRY(_START)');
|
||||
Add('MEMORY');
|
||||
Add('{');
|
||||
Add(' flash : ORIGIN = 0x08000000, LENGTH = 512K');
|
||||
Add(' ram : ORIGIN = 0x20000000, LENGTH = 64K');
|
||||
Add('}');
|
||||
Add('_stack_top = 0x2000FFFC;');
|
||||
end;
|
||||
ct_at91sam7xc256,
|
||||
|
||||
ct_stm32f103rb,
|
||||
ct_stm32f103re,
|
||||
|
||||
{ TI - 64 K Flash, 16 K SRAM Devices }
|
||||
ct_lm3s1110,
|
||||
ct_lm3s1133,
|
||||
ct_lm3s1138,
|
||||
ct_lm3s1150,
|
||||
ct_lm3s1162,
|
||||
ct_lm3s1165,
|
||||
ct_lm3s1166,
|
||||
ct_lm3s2110,
|
||||
ct_lm3s2139,
|
||||
ct_lm3s6100,
|
||||
ct_lm3s6110,
|
||||
|
||||
{ TI 128 K Flash, 32 K SRAM devices - Fury Class }
|
||||
ct_lm3s1601,
|
||||
ct_lm3s1608,
|
||||
ct_lm3s1620,
|
||||
ct_lm3s1635,
|
||||
ct_lm3s1636,
|
||||
ct_lm3s1637,
|
||||
ct_lm3s1651,
|
||||
ct_lm3s2601,
|
||||
ct_lm3s2608,
|
||||
ct_lm3s2620,
|
||||
ct_lm3s2637,
|
||||
ct_lm3s2651,
|
||||
ct_lm3s6610,
|
||||
ct_lm3s6611,
|
||||
ct_lm3s6618,
|
||||
ct_lm3s6633,
|
||||
ct_lm3s6637,
|
||||
ct_lm3s8630,
|
||||
|
||||
{ TI 256 K Flase, 32 K SRAM devices - Fury Class }
|
||||
ct_lm3s1911,
|
||||
ct_lm3s1918,
|
||||
ct_lm3s1937,
|
||||
ct_lm3s1958,
|
||||
ct_lm3s1960,
|
||||
ct_lm3s1968,
|
||||
ct_lm3s1969,
|
||||
ct_lm3s2911,
|
||||
ct_lm3s2918,
|
||||
ct_lm3s2919,
|
||||
ct_lm3s2939,
|
||||
ct_lm3s2948,
|
||||
ct_lm3s2950,
|
||||
ct_lm3s2965,
|
||||
ct_lm3s6911,
|
||||
ct_lm3s6918,
|
||||
ct_lm3s6938,
|
||||
ct_lm3s6950,
|
||||
ct_lm3s6952,
|
||||
ct_lm3s6965,
|
||||
ct_lm3s8930,
|
||||
ct_lm3s8933,
|
||||
ct_lm3s8938,
|
||||
ct_lm3s8962,
|
||||
ct_lm3s8970,
|
||||
ct_lm3s8971,
|
||||
|
||||
{ TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
|
||||
ct_lm3s5951,
|
||||
ct_lm3s5956,
|
||||
ct_lm3s1b21,
|
||||
ct_lm3s2b93,
|
||||
ct_lm3s5b91,
|
||||
ct_lm3s9b81,
|
||||
ct_lm3s9b90,
|
||||
ct_lm3s9b92,
|
||||
ct_lm3s9b95,
|
||||
ct_lm3s9b96,
|
||||
ct_thumb2bare:
|
||||
begin
|
||||
with embedded_controllers[current_settings.controllertype] do
|
||||
with linkres do
|
||||
begin
|
||||
Add('ENTRY(_START)');
|
||||
Add('MEMORY');
|
||||
Add('{');
|
||||
|
||||
LinkStr := ' flash : ORIGIN = 0x' + IntToHex(flashbase,8)
|
||||
+ ', LENGTH = ' + IntToStr(flashsize div 1024)+'K';
|
||||
Add(LinkStr);
|
||||
|
||||
LinkStr := ' ram : ORIGIN = 0x' + IntToHex(srambase,8)
|
||||
+ ', LENGTH = ' + IntToStr(sramsize div 1024)+'K';
|
||||
Add(LinkStr);
|
||||
|
||||
Add('}');
|
||||
Add('_stack_top = 0x' + IntToHex(sramsize+srambase-4,8) + ';');
|
||||
end;
|
||||
end
|
||||
else
|
||||
internalerror(200902011);
|
||||
if not (cs_link_nolink in current_settings.globalswitches) then
|
||||
internalerror(200902011);
|
||||
end;
|
||||
|
||||
with linkres do
|
||||
|
||||
@ -5,7 +5,7 @@ Geoffrey Barton 2010 08 01 gjb@periphon.net
|
||||
based on stm32f103 created by Jeppe Johansen 2009 - jepjoh2@kom.aau.dk
|
||||
}
|
||||
{$goto on}
|
||||
unit stellaris;
|
||||
unit lm3fury;
|
||||
|
||||
interface
|
||||
|
||||
297
rtl/embedded/arm/lm3tempest.pp
Normal file
297
rtl/embedded/arm/lm3tempest.pp
Normal file
@ -0,0 +1,297 @@
|
||||
{
|
||||
Register definitions and utility code for stellaris
|
||||
Preliminary startup code
|
||||
Geoffrey Barton 2010 08 01 gjb@periphon.net
|
||||
based on stm32f103 created by Jeppe Johansen 2009 - jepjoh2@kom.aau.dk
|
||||
}
|
||||
{$goto on}
|
||||
unit lm3tempest;
|
||||
|
||||
interface
|
||||
|
||||
type
|
||||
TBitvector32 = bitpacked array[0..31] of 0..1;
|
||||
|
||||
{$PACKRECORDS 4}
|
||||
const
|
||||
PeripheralBase = $40000000;
|
||||
PPBbase = $E0000fff;
|
||||
APBbase = PeripheralBase;
|
||||
AHBbase = PeripheralBase+$54000;
|
||||
portAoffset=APBbase+$4000;
|
||||
portBoffset=APBbase+$5000;
|
||||
portCoffset=APBbase+$6000;
|
||||
portDoffset=APBbase+$7000;
|
||||
portEoffset=APBbase+$24000;
|
||||
portFoffset=APBbase+$25000;
|
||||
portGoffset=APBbase+$26000;
|
||||
portHoffset=APBbase+$27000;
|
||||
portJoffset=APBbase+$3d000;
|
||||
sysconoffset=APBbase+$fe000;
|
||||
|
||||
|
||||
type
|
||||
TgpioPort=record
|
||||
data:array[0..255] of dword;dir,_is,ibe,iev,im,ris,mis,icr,
|
||||
afsel:dword;dummy1:array[0..54] of dword;dr2r,dr4r,dr8r,odr,pur,pdr,slr,den,lock,cr,amsel,pctl:dword;
|
||||
end;
|
||||
|
||||
Tsyscon=record
|
||||
did0,did1,dc0,res0c,dc1,dc2,dc3,dc4,dc5,dc6,dc7,dc8,borc,res34,res38,res3c,
|
||||
src0,src1,src2,res4c,ris,imc,misc,resc,rcc,pllcfg,res68,gpiohbctl,rcc2,res74,res78,moscctl:dword;res80:array[0..31] of dword;
|
||||
rcgc0,rcgc1,rcgc2,res10,scgc0,scgc1,scgc2,
|
||||
res11,dcgc0,dcgc1,dcgc2,res12c,res130,res134,res138,res13c,res140,dsplpclk,res13,res14,res15,piosccal,
|
||||
i2smclk,res174,res178,res17c,res180,res184,res188,res18c,dc9,res194,res198,res19c,nvmstat:dword;
|
||||
end;
|
||||
|
||||
{$ALIGN 4}
|
||||
var
|
||||
PortA :Tgpioport absolute portAoffset;
|
||||
PortB :Tgpioport absolute portBoffset;
|
||||
PortC :Tgpioport absolute portCoffset;
|
||||
PortD :Tgpioport absolute portDoffset;
|
||||
PortE :Tgpioport absolute portEoffset;
|
||||
PortF :Tgpioport absolute portFoffset;
|
||||
PortG :Tgpioport absolute portGoffset;
|
||||
PortH :Tgpioport absolute portHoffset;
|
||||
PortJ :Tgpioport absolute portJoffset;
|
||||
|
||||
syscon :Tsyscon absolute sysconoffset;
|
||||
rcgc0 :dword absolute (sysconoffset+$100);
|
||||
rcgc1 :dword absolute (sysconoffset+$104);
|
||||
rcgc2 :dword absolute (sysconoffset+$108);
|
||||
|
||||
|
||||
var
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
SWI_Handler,
|
||||
DebugMonitor_Handler,
|
||||
PendingSV_Handler,
|
||||
Systick_Handler,UART0intvector: pointer;
|
||||
|
||||
implementation
|
||||
|
||||
var
|
||||
_data: record end; external name '_data';
|
||||
_edata: record end; external name '_edata';
|
||||
_etext: record end; external name '_etext';
|
||||
_bss_start: record end; external name '_bss_start';
|
||||
_bss_end: record end; external name '_bss_end';
|
||||
_stack_top: record end; external name '_stack_top';
|
||||
|
||||
procedure PASCALMAIN; external name 'PASCALMAIN';
|
||||
|
||||
procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
|
||||
asm
|
||||
.Lhalt:
|
||||
b .Lhalt
|
||||
end;
|
||||
|
||||
|
||||
procedure _FPC_start; assembler; nostackframe;
|
||||
label
|
||||
_start;
|
||||
asm
|
||||
.init
|
||||
.align 16
|
||||
|
||||
// JEC NOTE: CONFIRMED AUG 2011 - address must manually have offset
|
||||
// the assembler / linker will NOT automatically add the LSB
|
||||
// failure to have the LSB prevents coming up in Thumb2 mode
|
||||
.long _stack_top // First entry in NVIC table is the new stack pointer
|
||||
.long _start+1 //gjb changed from stm32f version to avoid invstate error when interrupt fires
|
||||
//b _start // Reset
|
||||
.long _start+1
|
||||
//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
|
||||
.long _start+1
|
||||
//b .LHardFault_Addr // All class of fault
|
||||
.long _start+1
|
||||
//b .LMemManage_Addr // Memory management
|
||||
.long _start+1
|
||||
//b .LBusFault_Addr // Pre-fetch fault, memory access fault
|
||||
.long _start+1
|
||||
//b .LUsageFault_Addr // Undefined instruction or illegal state
|
||||
.long _start+1
|
||||
//nop // Reserved
|
||||
.long _start+1
|
||||
//nop // Reserved
|
||||
.long _start+1
|
||||
//nop // Reserved
|
||||
.long _start+1
|
||||
//nop // Reserved
|
||||
.long _start+1
|
||||
//b .LSWI_Addr // Software Interrupt vector now SVC
|
||||
.long _start+1
|
||||
//b .LDebugMonitor_Addr // Debug Monitor
|
||||
.long _start+1
|
||||
//nop // Reserved
|
||||
.long _start+1
|
||||
//b .LPendingSV_Addr // Pendable request for system service
|
||||
.long _start+1
|
||||
//b .LSystick_Addr // System tick timer
|
||||
//16
|
||||
.long .LDefaultHandler+1 //GPIOA #0
|
||||
.long .LDefaultHandler+1 //GPIOB
|
||||
.long .LDefaultHandler+1 //GPIOC
|
||||
.long .LDefaultHandler+1 //GPIOD
|
||||
.long .LDefaultHandler+1 //GPIOE
|
||||
.long .LUART0handler+1 //.LDefaultHandler+1 //UART0
|
||||
.long .LDefaultHandler+1 //UART1
|
||||
.long .LDefaultHandler+1 //SSI0
|
||||
//24
|
||||
.long .LDefaultHandler+1 //I2C0 #8
|
||||
.long .LDefaultHandler+1 //PWMF
|
||||
.long .LDefaultHandler+1 //PWMG0
|
||||
.long .LDefaultHandler+1 //PWMG1
|
||||
.long .LDefaultHandler+1 //PWMG2
|
||||
.long .LDefaultHandler+1 //QEI0
|
||||
.long .LDefaultHandler+1 //ADC0S0
|
||||
.long .LDefaultHandler+1 //ADC0S1
|
||||
//32
|
||||
.long .LDefaultHandler+1 //ADC0S2 #16
|
||||
.long .LDefaultHandler+1 //ADC0S3
|
||||
.long .LDefaultHandler+1 //WDGTimer01
|
||||
.long .LDefaultHandler+1 //T0A
|
||||
.long .LDefaultHandler+1 //T0B
|
||||
.long .LDefaultHandler+1 //T1A
|
||||
.long .LDefaultHandler+1 //T1B
|
||||
.long .LDefaultHandler+1 //T2A
|
||||
//40
|
||||
.long .LDefaultHandler+1 //T2B #24
|
||||
.long .LDefaultHandler+1 //COMP0
|
||||
.long .LDefaultHandler+1 //COMP1
|
||||
.long .LDefaultHandler+1 //COMP2
|
||||
.long .LDefaultHandler+1 //SYSCON
|
||||
.long .LDefaultHandler+1 //FLASH
|
||||
.long .LDefaultHandler+1 //GPIOF
|
||||
.long .LDefaultHandler+1 //GPIOG
|
||||
//48
|
||||
.long .LDefaultHandler+1 //GPIOH #32
|
||||
.long .LDefaultHandler+1 //UART2
|
||||
.long .LDefaultHandler+1 //SSI1
|
||||
.long .LDefaultHandler+1 //T3A
|
||||
.long .LDefaultHandler+1 //T3B
|
||||
.long .LDefaultHandler+1 //I2C1
|
||||
.long .LDefaultHandler+1 //QEI1
|
||||
.long .LDefaultHandler+1 //CAN0
|
||||
//56
|
||||
.long .LDefaultHandler+1 //CAN1 #40
|
||||
.long .LDefaultHandler+1 //res
|
||||
.long .LDefaultHandler+1 //ETH
|
||||
.long .LDefaultHandler+1 //res
|
||||
.long .LDefaultHandler+1 //USB
|
||||
.long .LDefaultHandler+1 //PWMG3
|
||||
.long .LDefaultHandler+1 //UDMAS
|
||||
.long .LDefaultHandler+1 //UDMAE
|
||||
//64
|
||||
.long .LDefaultHandler+1 //ADC1S0 #48
|
||||
.long .LDefaultHandler+1 //ADC1S1
|
||||
.long .LDefaultHandler+1 //ADC1S2
|
||||
.long .LDefaultHandler+1 //ADC1S3
|
||||
.long .LDefaultHandler+1 //I2S0
|
||||
.long .LDefaultHandler+1 //EPI
|
||||
.long .LDefaultHandler+1 //GPIOJ
|
||||
.long .LDefaultHandler+1 //res #55
|
||||
|
||||
.LNMI_Addr:
|
||||
ldr r0,.L1
|
||||
ldr pc,[r0]
|
||||
.LHardFault_Addr:
|
||||
ldr r0,.L2
|
||||
ldr pc,[r0]
|
||||
.LMemManage_Addr:
|
||||
ldr r0,.L3
|
||||
ldr pc,[r0]
|
||||
.LBusFault_Addr:
|
||||
ldr r0,.L4
|
||||
ldr pc,[r0]
|
||||
.LUsageFault_Addr:
|
||||
ldr r0,.L5
|
||||
ldr pc,[r0]
|
||||
.LSWI_Addr:
|
||||
ldr r0,.L6
|
||||
ldr pc,[r0]
|
||||
.LDebugMonitor_Addr:
|
||||
ldr r0,.L7
|
||||
ldr pc,[r0]
|
||||
.LPendingSV_Addr:
|
||||
ldr r0,.L8
|
||||
ldr pc,[r0]
|
||||
.LSystick_Addr:
|
||||
ldr r0,.L9
|
||||
ldr pc,[r0]
|
||||
.LUART0handler:
|
||||
ldr r0,.L10
|
||||
ldr pc,[r0]
|
||||
.L1:
|
||||
.long NMI_Handler
|
||||
.L2:
|
||||
.long HardFault_Handler
|
||||
.L3:
|
||||
.long MemManage_Handler
|
||||
.L4:
|
||||
.long BusFault_Handler
|
||||
.L5:
|
||||
.long UsageFault_Handler
|
||||
.L6:
|
||||
.long SWI_Handler
|
||||
.L7:
|
||||
.long DebugMonitor_Handler
|
||||
.L8:
|
||||
.long PendingSV_Handler
|
||||
.L9:
|
||||
.long Systick_Handler
|
||||
.L10:
|
||||
.long UART0IntVector
|
||||
|
||||
.globl _start
|
||||
.text
|
||||
_start:
|
||||
|
||||
// Copy initialized data to ram
|
||||
ldr r1,.L_etext
|
||||
ldr r2,.L_data
|
||||
ldr r3,.L_edata
|
||||
.Lcopyloop:
|
||||
cmp r2,r3
|
||||
ittt ls
|
||||
ldrls r0,[r1],#4
|
||||
strls r0,[r2],#4
|
||||
bls .Lcopyloop
|
||||
|
||||
// clear onboard ram
|
||||
ldr r1,.L_bss_start
|
||||
ldr r2,.L_bss_end
|
||||
mov r0,#0
|
||||
.Lzeroloop:
|
||||
cmp r1,r2
|
||||
itt ls
|
||||
strls r0,[r1],#4
|
||||
bls .Lzeroloop
|
||||
|
||||
b PASCALMAIN
|
||||
b _FPC_haltproc
|
||||
|
||||
.L_bss_start:
|
||||
.long _bss_start
|
||||
.L_bss_end:
|
||||
.long _bss_end
|
||||
.L_etext:
|
||||
.long _etext
|
||||
.L_data:
|
||||
.long _data
|
||||
.L_edata:
|
||||
.long _edata
|
||||
.LDefaultHandlerAddr:
|
||||
.long .LDefaultHandler
|
||||
// default irq handler just returns
|
||||
.LDefaultHandler:
|
||||
mov pc,r14
|
||||
end;
|
||||
|
||||
end.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user