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* patch by J. Gareth Moreton for less invasive DEBUG_AOPTCPU
git-svn-id: trunk@39239 -
This commit is contained in:
florian
parent
373061043b
commit
a0b343a787
@ -105,8 +105,15 @@ unit aoptx86;
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and having an offset }
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function MatchReferenceWithOffset(const ref : treference;base,index : TRegister) : Boolean;
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{$ifdef DEBUG_AOPTCPU}
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const
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SPeepholeOptimization: string = 'Peephole Optimization: ';
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SPeepholeOptimization: shortstring = 'Peephole Optimization: ';
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{$else DEBUG_AOPTCPU}
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{ Empty strings help the optimizer to remove string concatenations that won't
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ever appear to the user on release builds. [Kit] }
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const
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SPeepholeOptimization = '';
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{$endif DEBUG_AOPTCPU}
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implementation
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@ -485,10 +492,91 @@ unit aoptx86;
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begin
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asml.insertbefore(tai_comment.Create(strpnew(s)), p);
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end;
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function debug_tostr(i: tcgint): string; inline;
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begin
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Result := tostr(i);
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end;
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function debug_regname(r: TRegister): string; inline;
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begin
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Result := '%' + std_regname(r);
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end;
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{ Debug output function - creates a string representation of an operator }
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function debug_operstr(oper: TOper): string;
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begin
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case oper.typ of
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top_const:
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Result := '$' + debug_tostr(oper.val);
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top_reg:
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Result := debug_regname(oper.reg);
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top_ref:
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begin
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if oper.ref^.offset <> 0 then
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Result := debug_tostr(oper.ref^.offset) + '('
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else
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Result := '(';
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if (oper.ref^.base <> NR_INVALID) and (oper.ref^.base <> NR_NO) then
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begin
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Result := Result + debug_regname(oper.ref^.base);
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if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
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Result := Result + ',' + debug_regname(oper.ref^.index);
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end
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else
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if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
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Result := Result + debug_regname(oper.ref^.index);
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if (oper.ref^.scalefactor > 1) then
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Result := Result + ',' + debug_tostr(oper.ref^.scalefactor) + ')'
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else
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Result := Result + ')';
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end;
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else
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Result := '[UNKNOWN]';
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end;
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end;
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function debug_op2str(opcode: tasmop): string; inline;
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begin
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Result := std_op2str[opcode];
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end;
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function debug_opsize2str(opsize: topsize): string; inline;
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begin
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Result := gas_opsize2str[opsize];
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end;
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{$else DEBUG_AOPTCPU}
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procedure TX86AsmOptimizer.DebugMsg(const s: string;p : tai);inline;
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begin
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end;
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function debug_tostr(i: tcgint): string; inline;
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begin
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Result := '';
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end;
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function debug_regname(r: TRegister): string; inline;
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begin
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Result := '';
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end;
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function debug_operstr(oper: TOper): string; inline;
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begin
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Result := '';
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end;
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function debug_op2str(opcode: tasmop): string; inline;
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begin
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Result := '';
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end;
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function debug_opsize2str(opsize: topsize): string; inline;
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begin
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Result := '';
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end;
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{$endif DEBUG_AOPTCPU}
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@ -890,9 +978,9 @@ unit aoptx86;
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If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
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begin
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DebugMsg(SPeepholeOptimization + 'MovapXOpMovapX2Op ('+
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std_op2str[taicpu(p).opcode]+' '+
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std_op2str[taicpu(hp1).opcode]+' '+
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std_op2str[taicpu(hp2).opcode]+') done',p);
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debug_op2str(taicpu(p).opcode)+' '+
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debug_op2str(taicpu(hp1).opcode)+' '+
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debug_op2str(taicpu(hp2).opcode)+') done',p);
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{ we cannot eliminate the first move if
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the operations uses the same register for source and dest }
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if not(OpsEqual(taicpu(hp1).oper[1]^,taicpu(hp1).oper[0]^)) then
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@ -1118,12 +1206,8 @@ unit aoptx86;
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(getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
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then
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begin
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if taicpu(p).oper[0]^.typ = top_reg then
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InputVal := '%' + std_regname(taicpu(p).oper[0]^.reg)
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else
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InputVal := 'x';
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MaskNum := tostr(taicpu(hp1).oper[0]^.val);
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InputVal := debug_operstr(taicpu(p).oper[0]^);
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MaskNum := debug_tostr(taicpu(hp1).oper[0]^.val);
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case taicpu(p).opsize of
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S_B:
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@ -1137,8 +1221,8 @@ unit aoptx86;
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(Identical registers, just different sizes)
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}
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RegName1 := std_regname(taicpu(p).oper[1]^.reg); { 8-bit register name }
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RegName2 := std_regname(taicpu(hp1).oper[1]^.reg); { 16/32-bit register name }
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RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 8-bit register name }
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RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 16/32-bit register name }
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case taicpu(hp1).opsize of
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S_W: NewSize := S_BW;
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@ -1163,8 +1247,8 @@ unit aoptx86;
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(Identical registers, just different sizes)
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}
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RegName1 := std_regname(taicpu(p).oper[1]^.reg); { 16-bit register name }
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RegName2 := std_regname(taicpu(hp1).oper[1]^.reg); { 32-bit register name }
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RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 16-bit register name }
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RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 32-bit register name }
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case taicpu(hp1).opsize of
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S_L: NewSize := S_WL;
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@ -1183,7 +1267,7 @@ unit aoptx86;
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if NewSize <> S_NO then
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begin
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PreMessage := 'mov' + gas_opsize2str[taicpu(p).opsize] + ' ' + InputVal + ',%' + RegName1;
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PreMessage := 'mov' + debug_opsize2str(taicpu(p).opsize) + ' ' + InputVal + ',' + RegName1;
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{ The actual optimization }
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taicpu(p).opcode := A_MOVZX;
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@ -1201,12 +1285,12 @@ unit aoptx86;
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Peephole Optimizer. [Kit] }
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DebugMsg(SPeepholeOptimization + PreMessage +
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' -> movz' + gas_opsize2str[NewSize] + ' ' + InputVal + ',%' + RegName2, p);
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' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
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end
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else
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begin
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DebugMsg(SPeepholeOptimization + PreMessage + '; and' + gas_opsize2str[taicpu(hp1).opsize] + ' $' + MaskNum + ',%' + RegName2 +
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' -> movz' + gas_opsize2str[NewSize] + ' ' + InputVal + ',%' + RegName2, p);
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DebugMsg(SPeepholeOptimization + PreMessage + '; and' + debug_opsize2str(taicpu(hp1).opsize) + ' $' + MaskNum + ',' + RegName2 +
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' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
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asml.Remove(hp1);
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hp1.Free;
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@ -1667,9 +1751,9 @@ unit aoptx86;
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movw %ax,%si movw %ax,%si hp2
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}
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DebugMsg(SPeepholeOptimization + 'MovOpMov2Op ('+
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std_op2str[taicpu(p).opcode]+gas_opsize2str[taicpu(p).opsize]+' '+
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std_op2str[taicpu(hp1).opcode]+gas_opsize2str[taicpu(hp1).opsize]+' '+
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std_op2str[taicpu(hp2).opcode]+gas_opsize2str[taicpu(hp2).opsize],p);
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debug_op2str(taicpu(p).opcode)+debug_opsize2str(taicpu(p).opsize)+' '+
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debug_op2str(taicpu(hp1).opcode)+debug_opsize2str(taicpu(hp1).opsize)+' '+
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debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize),p);
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taicpu(hp1).changeopsize(taicpu(hp2).opsize);
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{
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->
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@ -3014,14 +3098,14 @@ unit aoptx86;
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case taicpu(p).opsize of
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S_Q:
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begin
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RegName := std_regname(taicpu(p).oper[1]^.reg); { 64-bit register name }
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Value := tostr(taicpu(p).oper[0]^.val);
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RegName := debug_regname(taicpu(p).oper[1]^.reg); { 64-bit register name }
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Value := debug_tostr(taicpu(p).oper[0]^.val);
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{ The actual optimization }
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setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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taicpu(p).changeopsize(S_L);
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DebugMsg(SPeepholeOptimization + 'movq $' + Value + ',%' + RegName + ' -> movl $' + Value + ',%' + std_regname(taicpu(p).oper[1]^.reg) + ' (immediate can be represented with just 32 bits)', p);
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DebugMsg(SPeepholeOptimization + 'movq $' + Value + ',' + RegName + ' -> movl $' + Value + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (immediate can be represented with just 32 bits)', p);
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Result := True;
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end;
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end;
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@ -3203,7 +3287,7 @@ unit aoptx86;
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then
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begin
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{ Has 64-bit register name and opcode suffix }
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PreMessage := 'movz' + gas_opsize2str[taicpu(p).opsize] + ' x,%' + std_regname(taicpu(p).oper[1]^.reg) + ' -> movz';
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PreMessage := 'movz' + debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' -> movz';
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{ The actual optimization }
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setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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@ -3213,7 +3297,7 @@ unit aoptx86;
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taicpu(p).changeopsize(S_WL);
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DebugMsg(SPeepholeOptimization + PreMessage +
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gas_opsize2str[taicpu(p).opsize] + ' x,%' + std_regname(taicpu(p).oper[1]^.reg) + ' (removes REX prefix)', p);
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debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (removes REX prefix)', p);
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end;
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end;
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@ -3238,17 +3322,17 @@ unit aoptx86;
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S_Q:
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if (getsupreg(taicpu(p).oper[0]^.reg) in [RS_RAX, RS_RCX, RS_RDX, RS_RBX, RS_RSI, RS_RDI, RS_RBP, RS_RSP]) then
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begin
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RegName := std_regname(taicpu(p).oper[0]^.reg); { 64-bit register name }
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PreMessage := 'xorq %' + RegName + ',%' + RegName + ' -> xorl %';
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RegName := debug_regname(taicpu(p).oper[0]^.reg); { 64-bit register name }
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PreMessage := 'xorq ' + RegName + ',' + RegName + ' -> xorl ';
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{ The actual optimization }
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setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
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setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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taicpu(p).changeopsize(S_L);
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RegName := std_regname(taicpu(p).oper[0]^.reg); { 32-bit register name }
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RegName := debug_regname(taicpu(p).oper[0]^.reg); { 32-bit register name }
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DebugMsg(SPeepholeOptimization + PreMessage + RegName + ',%' + RegName + ' (removes REX prefix)', p);
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DebugMsg(SPeepholeOptimization + PreMessage + RegName + ',' + RegName + ' (removes REX prefix)', p);
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end;
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end;
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end;
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