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Constrained a number of optimizations and updated reference offsets for ARM Thumb.

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Embedded target can now build with optimizations.

git-svn-id: trunk@28023 -
This commit is contained in:
Jeppe Johansen 2014-06-21 13:26:33 +00:00
parent 36d6fb7868
commit a1197460e1
3 changed files with 66 additions and 5 deletions

9
compiler/arm/aoptcpu.pas
View File

@ -1206,6 +1206,12 @@ Implementation
(taicpu(hp1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg))
) and
not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) and
// Make sure that Thumb code doesn't propagate a high register into a reference
((GenerateThumbCode and
(getsupreg(taicpu(p).oper[1]^.reg) < RS_R8)) or
(not GenerateThumbCode)) and
RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hp1)) then
begin
DebugMsg('Peephole MovLdr2Ldr done', hp1);
@ -1600,7 +1606,8 @@ Implementation
to
str/ldr reg3,[reg1,const2+/-const1]
}
if (taicpu(p).opcode in [A_ADD,A_SUB]) and
if (not GenerateThumbCode) and
(taicpu(p).opcode in [A_ADD,A_SUB]) and
(taicpu(p).ops>2) and
(taicpu(p).oper[1]^.typ = top_reg) and
(taicpu(p).oper[2]^.typ = top_const) then

58
compiler/arm/cgcpu.pas
View File

@ -181,6 +181,8 @@ unit cgcpu;
procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; reg: tregister);override;
procedure g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint); override;
function handle_load_store(list: TAsmList; op: tasmop; oppostfix: toppostfix; reg: tregister; ref: treference): treference; override;
end;
tthumbcg64farm = class(tbasecg64farm)
@ -3866,8 +3868,8 @@ unit cgcpu;
{ only complicated references need an extra loadaddr }
if assigned(ref.symbol) or
(ref.index<>NR_NO) or
(ref.offset<-255) or
(ref.offset>4094) or
(ref.offset<-124) or
(ref.offset>124) or
{ sometimes the compiler reused registers }
(reg=ref.index) or
(reg=ref.base) then
@ -3899,8 +3901,8 @@ unit cgcpu;
{ only complicated references need an extra loadaddr }
if assigned(ref.symbol) or
(ref.index<>NR_NO) or
(ref.offset<-255) or
(ref.offset>4092) or
(ref.offset<-124) or
(ref.offset>124) or
{ sometimes the compiler reused registers }
(reg=ref.index) or
(reg=ref.base) then
@ -4049,6 +4051,54 @@ unit cgcpu;
end;
function tthumbcgarm.handle_load_store(list: TAsmList; op: tasmop; oppostfix: toppostfix; reg: tregister; ref: treference): treference;
var
href : treference;
tmpreg : TRegister;
begin
href:=ref;
if (op in [A_STR,A_STRB,A_STRH]) and
(abs(ref.offset)>124) then
begin
tmpreg:=getintregister(list,OS_ADDR);
a_loadaddr_ref_reg(list,ref,tmpreg);
reference_reset_base(href,tmpreg,0,ref.alignment);
end
else if (op=A_LDR) and
(oppostfix in [PF_None]) and
(ref.base<>NR_STACK_POINTER_REG) and
(abs(ref.offset)>124) then
begin
tmpreg:=getintregister(list,OS_ADDR);
a_loadaddr_ref_reg(list,ref,tmpreg);
reference_reset_base(href,tmpreg,0,ref.alignment);
end
else if (op=A_LDR) and
(oppostfix in [PF_None]) and
(ref.base=NR_STACK_POINTER_REG) and
(abs(ref.offset)>1020) then
begin
tmpreg:=getintregister(list,OS_ADDR);
a_loadaddr_ref_reg(list,ref,tmpreg);
reference_reset_base(href,tmpreg,0,ref.alignment);
end
else if (op=A_LDR) and
((oppostfix in [PF_SH,PF_SB]) or
(abs(ref.offset)>124)) then
begin
tmpreg:=getintregister(list,OS_ADDR);
a_loadaddr_ref_reg(list,ref,tmpreg);
reference_reset_base(href,tmpreg,0,ref.alignment);
end;
Result:=inherited handle_load_store(list, op, oppostfix, reg, href);
end;
procedure tthumbcgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
var
tmpreg,overflowreg : tregister;

4
compiler/arm/rgcpu.pas
View File

@ -290,6 +290,10 @@ unit rgcpu;
if abs(spilltemp.offset)>4095 then
exit;
if GenerateThumbCode and
(abs(spilltemp.offset)>1020) then
exit;
{ Replace 'mov dst,orgreg' with 'ldr dst,spilltemp'
and 'mov orgreg,src' with 'str dst,spilltemp' }
with instr do