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m68k: fixed and enabled hardware mod/div support for coldfire, also it no longer depends on cpu family but cpu capability

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git-svn-id: trunk@33821 -
This commit is contained in:
Károly Balogh 2016-05-26 16:54:39 +00:00
parent 931c14f0cf
commit a2a630e9c5
4 changed files with 21 additions and 22 deletions
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2
compiler/m68k/aasmcpu.pas
View File

@ -498,7 +498,7 @@ type
A_ADD, A_ADDQ, A_ADDX, A_SUB, A_SUBQ, A_SUBX,
A_AND, A_LSR, A_LSL, A_ASR, A_ASL, A_EOR, A_EORI, A_OR,
A_ROL, A_ROR, A_ROXL, A_ROXR,
A_MULS, A_MULU, A_DIVS, A_DIVU, A_DIVSL, A_DIVUL,
A_MULS, A_MULU, A_DIVS, A_DIVU, A_DIVSL, A_DIVUL, A_REMS, A_REMU,
A_BSET, A_BCLR:
if opnr=1 then
result:=operand_readwrite;

2
compiler/m68k/cpubase.pas
View File

@ -67,7 +67,7 @@ unit cpubase;
{ mc64040 instructions }
a_move16,
{ coldfire v4 instructions }
a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,
a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,a_remu,a_rems,
{ fpu processor instructions - directly supported }
{ ieee aware and misc. condition codes not supported }
a_fabs,a_fadd,

2
compiler/m68k/itcpugas.pas
View File

@ -61,7 +61,7 @@ interface
{ mc64040 instructions }
'move16',
{ coldfire v4 instructions }
'mov3q','mvz','mvs','sats','byterev','ff1',
'mov3q','mvz','mvs','sats','byterev','ff1','remu','rems',
{ fpu processor instructions - directly supported }
{ ieee aware and misc. condition codes not supported }
'fabs','fadd',

37
compiler/m68k/n68kmat.pas
View File

@ -142,7 +142,7 @@ implementation
function tm68kmoddivnode.first_moddivint: tnode;
begin
if current_settings.cputype in cpu_mc68020p then
if CPUM68K_HAS_32BITDIV in cpu_capabilities[current_settings.cputype] then
result:=nil
else
result:=inherited first_moddivint;
@ -150,13 +150,12 @@ implementation
procedure tm68kmoddivnode.emit_div_reg_reg(signed: boolean;denum,num : tregister);
const
divudivs: array[boolean] of tasmop = (A_DIVU,A_DIVS);
begin
if current_settings.cputype in cpu_mc68020p then
if CPUM68K_HAS_32BITDIV in cpu_capabilities[current_settings.cputype] then
begin
if signed then
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_DIVS,S_L,denum,num))
else
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_DIVU,S_L,denum,num));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(divudivs[signed],S_L,denum,num));
end
else
InternalError(2014062801);
@ -164,22 +163,22 @@ implementation
procedure tm68kmoddivnode.emit_mod_reg_reg(signed: boolean;denum,num : tregister);
const
remop: array[boolean,boolean] of tasmop = ((A_DIVU,A_DIVS),(A_REMU,A_REMS));
var
tmpreg : tregister;
begin
if current_settings.cputype in cpu_mc68020p then
begin
tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
{ copy the numerator to the tmpreg, so we can use it as quotient, which
means we'll get the remainder immediately in the numerator }
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,num,tmpreg);
if signed then
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIVSL,S_L,denum,num,tmpreg))
else
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIVUL,S_L,denum,num,tmpreg));
end
else
InternalError(2014062802);
if CPUM68K_HAS_32BITDIV in cpu_capabilities[current_settings.cputype] then
begin
tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
{ copy the numerator to the tmpreg, so we can use it as quotient, which
means we'll get the remainder immediately in the numerator }
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,num,tmpreg);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(
remop[CPUM68K_HAS_REMSREMU in cpu_capabilities[current_settings.cputype],signed],S_L,denum,num,tmpreg));
end
else
InternalError(2014062802);
end;