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+ Risc-V: make use of zext.h if available
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5186044e81
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a53eb8b230
@ -129,6 +129,10 @@ unit cgcpu;
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list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
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else if (tosize=OS_8) and (fromsize<>OS_8) then
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list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
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else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_16) then
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list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
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else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_16) and (fromsize<>OS_16) then
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list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
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else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
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{ do we need to mask out the sign when loading from smaller signed to larger unsigned type? }
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@ -206,7 +206,7 @@ Const
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CPURV_HAS_COMPACT,
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CPURV_HAS_16REGISTERS,
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CPURV_HAS_ZBA,
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CPURV_HAS_ZBb,
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CPURV_HAS_ZBB,
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CPURV_HAS_ZBC,
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CPURV_HAS_ZBS,
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CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }
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@ -108,6 +108,10 @@ implementation
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list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
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else if (tosize=OS_8) and (fromsize<>OS_8) then
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list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
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else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_16) then
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list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
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else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_16) and (fromsize<>OS_16) then
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list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
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else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
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{ do we need to mask out the sign when loading from smaller signed to larger unsigned type? }
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@ -124,7 +124,7 @@ Const
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CPURV_HAS_ATOMIC,
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CPURV_HAS_COMPACT,
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CPURV_HAS_ZBA,
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CPURV_HAS_ZBb,
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CPURV_HAS_ZBB,
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CPURV_HAS_ZBC,
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CPURV_HAS_ZBS,
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CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }
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