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+ Risc-V: make use of zext.h if available

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florian 2024-08-14 22:37:02 +02:00
parent 5186044e81
commit a53eb8b230
4 changed files with 10 additions and 2 deletions
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4
compiler/riscv32/cgcpu.pas
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@ -129,6 +129,10 @@ unit cgcpu;
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF)) list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (tosize=OS_8) and (fromsize<>OS_8) then else if (tosize=OS_8) and (fromsize<>OS_8) then
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF)) list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_16) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_16) and (fromsize<>OS_16) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or ((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
{ do we need to mask out the sign when loading from smaller signed to larger unsigned type? } { do we need to mask out the sign when loading from smaller signed to larger unsigned type? }

2
compiler/riscv32/cpuinfo.pas
View File

@ -206,7 +206,7 @@ Const
CPURV_HAS_COMPACT, CPURV_HAS_COMPACT,
CPURV_HAS_16REGISTERS, CPURV_HAS_16REGISTERS,
CPURV_HAS_ZBA, CPURV_HAS_ZBA,
CPURV_HAS_ZBb, CPURV_HAS_ZBB,
CPURV_HAS_ZBC, CPURV_HAS_ZBC,
CPURV_HAS_ZBS, CPURV_HAS_ZBS,
CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr } CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }

4
compiler/riscv64/cgcpu.pas
View File

@ -108,6 +108,10 @@ implementation
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF)) list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (tosize=OS_8) and (fromsize<>OS_8) then else if (tosize=OS_8) and (fromsize<>OS_8) then
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF)) list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_16) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_16) and (fromsize<>OS_16) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or ((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
{ do we need to mask out the sign when loading from smaller signed to larger unsigned type? } { do we need to mask out the sign when loading from smaller signed to larger unsigned type? }

2
compiler/riscv64/cpuinfo.pas
View File

@ -124,7 +124,7 @@ Const
CPURV_HAS_ATOMIC, CPURV_HAS_ATOMIC,
CPURV_HAS_COMPACT, CPURV_HAS_COMPACT,
CPURV_HAS_ZBA, CPURV_HAS_ZBA,
CPURV_HAS_ZBb, CPURV_HAS_ZBB,
CPURV_HAS_ZBC, CPURV_HAS_ZBC,
CPURV_HAS_ZBS, CPURV_HAS_ZBS,
CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr } CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }