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patches by Nico Erfurth to improve the arm peephole optimizer:
* Introduce MatchInstruction and MatchOperand MatchInstruction allows to match an instruction by condition and oppostfix. MatchOperand checks if an operand is a register and matches another operand. In the future this could be overloaded with other versions not only accepting TRegister. * Optimize cmp,moveq,movne sequence on ARM This patch implements an peephole optimizer for the following sequence: cmp reg,const1 movne reg,const2 moveq reg,const1 * Small improvements to the ARM peephole optimizer Most instructions in the ARM ISA have taicpu(p).oper[0]^.typ = top_reg as the only option, so there is no need to check for it if we're looking at those instructions. * Remove redundant mov instructions on ARM This is an addition to the ARM PeepHole Optimizer. It folds code like this: mov reg1, reg2 add reg1, reg1, (const|reg) git-svn-id: trunk@21024 -
This commit is contained in:
florian
parent
7800cd4ff5
commit
aa2a9dbf2e
@ -78,11 +78,36 @@ Implementation
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(r1.shiftmode = r2.shiftmode);
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end;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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(taicpu(instr).opcode = op) and
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((cond = []) or (taicpu(instr).condition in cond)) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
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begin
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result := (oper.typ = top_reg) and (oper.reg = reg);
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end;
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procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList) ;
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begin
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if (taicpu(movp).condition = C_EQ) and
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(taicpu(cmpp).oper[0]^.reg = taicpu(movp).oper[0]^.reg) and
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(taicpu(cmpp).oper[1]^.val = taicpu(movp).oper[1]^.val) then
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begin
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asml.insertafter(tai_comment.Create(strpnew('Peephole CmpMovMov - Removed redundant moveq')), movp);
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asml.remove(movp);
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movp.free;
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end;
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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next1: tai;
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hp1,hp2: tai;
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i: longint;
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begin
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result := false;
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case p.typ of
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@ -99,15 +124,10 @@ Implementation
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{ this optimization can applied only to the currently enabled operations because
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the other operations do not update all flags and FPC does not track flag usage }
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if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oppostfix = PF_None) and
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(taicpu(p).condition = C_None) and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_CMP) and
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(taicpu(hp1).oppostfix = PF_None) and
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(taicpu(hp1).condition = C_None) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchInstruction(hp1, A_CMP, [C_None], [PF_None]) and
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(taicpu(hp1).oper[1]^.typ = top_const) and
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.val = 0) { and
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@ -136,11 +156,8 @@ Implementation
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_LDR) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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((taicpu(p).condition = taicpu(hp1).condition) or
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(taicpu(p).condition = C_None)) and
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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begin
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if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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@ -150,6 +167,7 @@ Implementation
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end
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else
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole StrLdr2StrMov done')), hp1);
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taicpu(hp1).opcode:=A_MOV;
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taicpu(hp1).oppostfix:=PF_None;
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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@ -168,22 +186,21 @@ Implementation
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_LDR) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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((taicpu(p).condition = taicpu(hp1).condition) or
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(taicpu(p).condition = C_None)) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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begin
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if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2Ldr done')), hp1);
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asml.remove(hp1);
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hp1.free;
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end
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else
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2LdrMov done')), hp1);
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taicpu(hp1).opcode:=A_MOV;
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taicpu(hp1).oppostfix:=PF_None;
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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@ -200,23 +217,18 @@ Implementation
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mov reg1,reg0, shift imm1+imm2
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}
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if (taicpu(p).ops=3) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
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getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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(taicpu(next1).opcode = A_MOV) and
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(taicpu(p).condition=taicpu(next1).condition) and
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(taicpu(next1).ops=3) and
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(taicpu(next1).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[0]^.reg) and
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(taicpu(next1).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[1]^.reg) and
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(taicpu(next1).oper[2]^.typ = top_shifterop) and
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(taicpu(next1).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(next1).oper[2]^.shifterop^.shiftmode) then
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getnextinstruction(p,hp1) and
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MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and
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(taicpu(hp1).ops=3) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[2]^.typ = top_shifterop) and
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(taicpu(hp1).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(hp1).oper[2]^.shifterop^.shiftmode) then
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begin
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inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(next1).oper[2]^.shifterop^.shiftimm);
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inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(hp1).oper[2]^.shifterop^.shiftimm);
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{ avoid overflows }
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if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
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case taicpu(p).oper[2]^.shifterop^.shiftmode of
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@ -235,10 +247,50 @@ Implementation
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else
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internalerror(2008072803);
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end;
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asml.remove(next1);
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next1.free;
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asml.insertbefore(tai_comment.Create(strpnew('Peephole ShiftShift2Shift done')), p);
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asml.remove(hp1);
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hp1.free;
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result := true;
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end;
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{
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change
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mov r1, r0
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add r1, r1, #1
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to
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add r1, r0, #1
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}
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if (taicpu(p).ops = 2) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oppostfix = PF_NONE) and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode in [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
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A_AND, A_BIC, A_EOR, A_ORR]) and
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(taicpu(hp1).condition in [C_NONE, taicpu(hp1).condition]) and
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MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(taicpu(hp1).oper[2]^.typ in [top_reg, top_const]) then
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begin
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{ When we get here we still don't know if the registers match}
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for I:=1 to 2 do
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{
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If the first loop was successful p will be replaced with hp1.
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The checks will still be ok, because all required information
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will also be in hp1 then.
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}
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if MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole RedundantMovProcess done ')), hp1);
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taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
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if p<>hp1 then
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begin
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asml.remove(p);
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p.free;
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p:=hp1;
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end;
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end;
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end;
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end;
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A_AND:
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begin
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@ -249,26 +301,44 @@ Implementation
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to
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and reg2,reg1,(const1 and const2)
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}
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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if (taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_AND) and
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(taicpu(p).condition=taicpu(hp1).condition) and
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(taicpu(p).oppostfix=PF_None) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(taicpu(hp1).oper[2]^.typ = top_const) and
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
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MatchInstruction(hp1, A_AND, [taicpu(p).condition], [PF_None]) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[2]^.typ = top_const) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole AndAnd2And done')), p);
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taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
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taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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A_CMP:
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begin
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{
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change
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cmp reg,const1
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moveq reg,const1
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movne reg,const2
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to
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cmp reg,const1
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movne reg,const2
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}
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if (taicpu(p).oper[1]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
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(taicpu(hp1).oper[1]^.typ = top_const) and
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GetNextInstruction(hp1, hp2) and
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MatchInstruction(hp2, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
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(taicpu(hp1).oper[1]^.typ = top_const) then
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begin
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RemoveRedundantMove(p, hp1, asml);
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RemoveRedundantMove(p, hp2, asml);
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end;
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end;
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end;
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end;
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end;
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@ -137,6 +137,8 @@ unit cpubase;
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PF_IAX,PF_DBX,PF_FDX,PF_EAX
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);
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TOpPostfixes = set of TOpPostfix;
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TRoundingMode = (RM_None,RM_P,RM_M,RM_Z);
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const
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@ -167,6 +169,8 @@ unit cpubase;
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C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
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);
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TAsmConds = set of TAsmCond;
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const
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cond2str : array[TAsmCond] of string[2]=('',
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'eq','ne','cs','cc','mi','pl','vs','vc','hi','ls',
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