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+ MIPS: make use of instructions MUL,SEB and SEH that are available in modern cores.

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git-svn-id: trunk@28590 -
This commit is contained in:
sergei 2014-09-03 19:59:00 +00:00
parent 64769b847a
commit ac64c4600f
1 changed files with 38 additions and 20 deletions
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20
compiler/mips/cgcpu.pas
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@ -436,7 +436,7 @@ end;
procedure TCGMIPS.a_load_const_reg(list: tasmlist; size: TCGSize; a: tcgint; reg: TRegister); procedure TCGMIPS.a_load_const_reg(list: tasmlist; size: TCGSize; a: tcgint; reg: TRegister);
begin begin
if (a = 0) then if (a = 0) then
list.concat(taicpu.op_reg_reg(A_MOVE, reg, NR_R0)) a_load_reg_reg(list, OS_INT, OS_INT, NR_R0, reg)
else if (a >= simm16lo) and (a <= simm16hi) then else if (a >= simm16lo) and (a <= simm16hi) then
list.concat(taicpu.op_reg_reg_const(A_ADDIU, reg, NR_R0, a)) list.concat(taicpu.op_reg_reg_const(A_ADDIU, reg, NR_R0, a))
else if (a>=0) and (a <= 65535) then else if (a>=0) and (a <= 65535) then
@ -540,15 +540,25 @@ begin
OS_S32: OS_S32:
done:=false; done:=false;
OS_S8: OS_S8:
begin
if (CPUMIPS_HAS_ISA32R2 in cpu_capabilities[current_settings.cputype]) then
list.concat(taicpu.op_reg_reg(A_SEB,reg2,reg1))
else
begin begin
list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 24)); list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 24));
list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 24)); list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 24));
end; end;
end;
OS_S16: OS_S16:
begin
if (CPUMIPS_HAS_ISA32R2 in cpu_capabilities[current_settings.cputype]) then
list.concat(taicpu.op_reg_reg(A_SEH,reg2,reg1))
else
begin begin
list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 16)); list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 16));
list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 16)); list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 16));
end; end;
end;
else else
internalerror(2002090901); internalerror(2002090901);
end; end;
@ -815,6 +825,7 @@ var
hreg: TRegister; hreg: TRegister;
asmop: TAsmOp; asmop: TAsmOp;
begin begin
a:=aint(a);
ovloc.loc := LOC_VOID; ovloc.loc := LOC_VOID;
optimize_op_const(size,op,a); optimize_op_const(size,op,a);
signed:=(size in [OS_S8,OS_S16,OS_S32]); signed:=(size in [OS_S8,OS_S16,OS_S32]);
@ -929,6 +940,12 @@ begin
a_load_reg_reg(list, OS_INT, OS_INT, hreg, dst); a_load_reg_reg(list, OS_INT, OS_INT, hreg, dst);
end; end;
OP_MUL,OP_IMUL: OP_MUL,OP_IMUL:
begin
if (CPUMIPS_HAS_ISA32R2 in cpu_capabilities[current_settings.cputype]) and
(not setflags) then
{ NOTE: MUL is actually mips32r1 instruction; on older cores it is handled as macro }
list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src2,src1))
else
begin begin
list.concat(taicpu.op_reg_reg(TOpCg2AsmOp[op], src2, src1)); list.concat(taicpu.op_reg_reg(TOpCg2AsmOp[op], src2, src1));
list.concat(taicpu.op_reg(A_MFLO, dst)); list.concat(taicpu.op_reg(A_MFLO, dst));
@ -949,6 +966,7 @@ begin
a_label(list,hl); a_label(list,hl);
end; end;
end; end;
end;
OP_AND,OP_OR,OP_XOR: OP_AND,OP_OR,OP_XOR:
begin begin
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op], dst, src2, src1)); list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op], dst, src2, src1));