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* some RiscV optimizer improvements and fixes
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@ -439,7 +439,7 @@ implementation
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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((MatchInstruction(hp1, [A_SUB,A_ADD,A_SLL,A_SRL,A_SLT,A_AND,A_OR,
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A_ADDI,A_ANDI,A_ORI,A_SRAI,A_SRLI,A_SLLI,A_XORI,A_MUL,
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A_DIV,A_DIVU,A_REM,A_REMU
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A_DIV,A_DIVU,A_REM,A_REMU,A_SLTI,A_SLTIU
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{$ifdef riscv64},A_ADDIW,A_SLLIW,A_SRLIW,A_SRAIW,
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A_ADDW,A_SLLW,A_SRLW,A_SUBW,A_SRAW,
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A_DIVUW,A_DIVW,A_REMW,A_REMUW{$endif}]
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@ -650,6 +650,7 @@ implementation
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RemoveInstr(p);
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result:=true;
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exit;
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end
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else if MatchInstruction(hp1,A_ANDI) and
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(taicpu(hp1).ops=3) and
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@ -665,8 +666,11 @@ implementation
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RemoveInstr(hp1);
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result:=true;
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exit;
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end;
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end;
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{ in all other branches we exit before }
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result:=OptPass1OP(p);
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end;
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@ -749,6 +753,9 @@ implementation
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(taicpu(p).oper[2]^.val=1) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) then
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begin
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{
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we cannot do this optimization yet as we don't know if taicpu(p).oper[0]^.reg isn't used after taking the branch
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if MatchInstruction(hp1,A_Bxx,[C_NE,C_EQ]) and
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(taicpu(hp1).ops=3) and
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MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^) and
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@ -764,8 +771,9 @@ implementation
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RemoveInstr(p);
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result:=true;
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exit;
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end
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else if MatchInstruction(hp1,A_ANDI) and
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else } if MatchInstruction(hp1,A_ANDI) and
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(taicpu(hp1).ops=3) and
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(taicpu(hp1).oper[2]^.val>0) and
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MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) and
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@ -779,8 +787,11 @@ implementation
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RemoveInstr(hp1);
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result:=true;
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exit;
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end;
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end;
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{ in all other branches we exit before }
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result:=OptPass1OP(p);
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end;
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