* unified Risc-V 32 and 64 register data file

compiler/riscv64/rv32reg.dat

@@ -1,77 +0,0 @@
-;
-; RiscV registers
-;
-; layout
-; <name>,<type>,<subtype>,<value>,<stdname>,<stab idx>,<dwarf idx>
-;
-NO,$00,$00,$00,INVALID,-1,-1
-; Integer registers
-X0,$01,$00,$00,x0,0,0
-X1,$01,$00,$01,x1,1,1
-X2,$01,$00,$02,x2,2,2
-X3,$01,$00,$03,x3,3,3
-X4,$01,$00,$04,x4,4,4
-X5,$01,$00,$05,x5,5,5
-X6,$01,$00,$06,x6,6,6
-X7,$01,$00,$07,x7,7,7
-X8,$01,$00,$08,x8,8,8
-X9,$01,$00,$09,x9,9,9
-X10,$01,$00,$0a,x10,10,10
-X11,$01,$00,$0b,x11,11,11
-X12,$01,$00,$0c,x12,12,12
-X13,$01,$00,$0d,x13,13,13
-X14,$01,$00,$0e,x14,14,14
-X15,$01,$00,$0f,x15,15,15
-X16,$01,$00,$10,x16,16,16
-X17,$01,$00,$11,x17,17,17
-X18,$01,$00,$12,x18,18,18
-X19,$01,$00,$13,x19,19,19
-X20,$01,$00,$14,x20,20,20
-X21,$01,$00,$15,x21,21,21
-X22,$01,$00,$16,x22,22,22
-X23,$01,$00,$17,x23,23,23
-X24,$01,$00,$18,x24,24,24
-X25,$01,$00,$19,x25,25,25
-X26,$01,$00,$1a,x26,26,26
-X27,$01,$00,$1b,x27,27,27
-X28,$01,$00,$1c,x28,28,28
-X29,$01,$00,$1d,x29,29,29
-X30,$01,$00,$1e,x30,30,30
-X31,$01,$00,$1f,x31,31,31
-
-; Float registers
-F0,$02,$00,$00,f0,0,0
-F1,$02,$00,$01,f1,1,1
-F2,$02,$00,$02,f2,2,2
-F3,$02,$00,$03,f3,3,3
-F4,$02,$00,$04,f4,4,4
-F5,$02,$00,$05,f5,5,5
-F6,$02,$00,$06,f6,6,6
-F7,$02,$00,$07,f7,7,7
-F8,$02,$00,$08,f8,8,8
-F9,$02,$00,$09,f9,9,9
-F10,$02,$00,$0a,f10,10,10
-F11,$02,$00,$0b,f11,11,11
-F12,$02,$00,$0c,f12,12,12
-F13,$02,$00,$0d,f13,13,13
-F14,$02,$00,$0e,f14,14,14
-F15,$02,$00,$0f,f15,15,15
-F16,$02,$00,$10,f16,16,16
-F17,$02,$00,$11,f17,17,17
-F18,$02,$00,$12,f18,18,18
-F19,$02,$00,$13,f19,19,19
-F20,$02,$00,$14,f20,20,20
-F21,$02,$00,$15,f21,21,21
-F22,$02,$00,$16,f22,22,22
-F23,$02,$00,$17,f23,23,23
-F24,$02,$00,$18,f24,24,24
-F25,$02,$00,$19,f25,25,25
-F26,$02,$00,$1a,f26,26,26
-F27,$02,$00,$1b,f27,27,27
-F28,$02,$00,$1c,f28,28,28
-F29,$02,$00,$1d,f29,29,29
-F30,$02,$00,$1e,f30,30,30
-F31,$02,$00,$1f,f31,31,31
-
-; Special registers
-FCSR,$05,$00,$01,fcsr,0,0