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* sparc: overflow support for 64 bit operations

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This commit is contained in:
florian 2024-04-02 16:41:38 +02:00
parent 80e8dce98f
commit b00e9543a7
2 changed files with 20 additions and 2 deletions
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16
compiler/sparc/cgcpu.pas
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@ -273,6 +273,14 @@ interface
tcgsparc(cg).handle_reg_const_reg(list,op1,regsrc.reglo,tcgint(lo(value)),regdst.reglo);
tcgsparc(cg).handle_reg_const_reg(list,op2,regsrc.reghi,tcgint(hi(value)),regdst.reghi);
end;
if setflags then
begin
ovloc.loc:=LOC_FLAGS;
ovloc.resflags.Init(NR_ICC,F_VS);
end
else
ovloc.loc:=LOC_INVALID;
end;
@ -290,6 +298,14 @@ interface
get_64bit_ops(op,op1,op2,setflags);
list.concat(taicpu.op_reg_reg_reg(op1,regsrc2.reglo,regsrc1.reglo,regdst.reglo));
list.concat(taicpu.op_reg_reg_reg(op2,regsrc2.reghi,regsrc1.reghi,regdst.reghi));
if setflags then
begin
ovloc.loc:=LOC_FLAGS;
ovloc.resflags.Init(NR_ICC,F_VS);
end
else
ovloc.loc:=LOC_INVALID;
end;

6
compiler/sparcgen/cpubase.pas
View File

@ -186,6 +186,8 @@ uses
F_AE, {Above or Equal, synonym: Carry Clear}
F_B, {Below, synonym: Carry Set}
F_BE, {Below or Equal}
F_VC, {No Overflow}
F_VS, {Overflow}
{ Floating point results }
F_FE, {Equal}
F_FNE, {Not Equal}
@ -398,7 +400,7 @@ implementation
procedure inverse_flags(var f: TResFlags);
const
inv_flags: array[TSparcFlags] of TSparcFlags =
(F_NE,F_E,F_LE,F_GE,F_L,F_G,F_BE,F_B,F_AE,F_A,
(F_NE,F_E,F_LE,F_GE,F_L,F_G,F_BE,F_B,F_AE,F_A,F_VS,F_VC,
F_FNE,F_FE,F_FLE,F_FGE,F_FL,F_FG);
begin
f.Flags:=inv_flags[f.Flags];
@ -408,7 +410,7 @@ implementation
function flags_to_cond(const f:TResFlags):TAsmCond;
const
flags_2_cond:array[TSparcFlags] of TAsmCond=
(C_E,C_NE,C_G,C_L,C_GE,C_LE,C_A,C_AE,C_B,C_BE,
(C_E,C_NE,C_G,C_L,C_GE,C_LE,C_A,C_AE,C_B,C_BE,C_VC,C_VS,
C_FE,C_FNE,C_FG,C_FL,C_FGE,C_FLE);
begin
result:=flags_2_cond[f.Flags];