+ OpCmp2Op optimization for AVR

git-svn-id: trunk@31013 -

compiler/avr/aoptcpu.pas

@@ -49,6 +49,9 @@ Implementation
     globals,globtype,
     cgutils;
 
+  type
+    TAsmOpSet = set of TAsmOp;
+
   function CanBeCond(p : tai) : boolean;
     begin
       result:=(p.typ=ait_instruction) and (taicpu(p).condition=C_None);
@@ -98,6 +101,14 @@ Implementation
     end;
 
 
+  function MatchInstruction(const instr: tai; const ops: TAsmOpSet): boolean;
+    begin
+      result :=
+        (instr.typ = ait_instruction) and
+        (taicpu(instr).opcode in ops);
+    end;
+
+
   function TCpuAsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
     begin
       If (p1.typ = ait_instruction) and (taicpu(p1).opcode in [A_MUL,A_MULS,A_FMUL,A_FMULS,A_FMULSU]) and
@@ -129,6 +140,51 @@ Implementation
       case p.typ of
         ait_instruction:
           begin
+            {
+              change
+              <op> reg,x,y
+              cp reg,r1
+              into
+              <op>s reg,x,y
+            }
+            { this optimization can applied only to the currently enabled operations because
+              the other operations do not update all flags and FPC does not track flag usage }
+            if MatchInstruction(p, [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_DEC,A_EOR,
+                                    A_INC,A_LSL,A_LSR,
+                                    A_OR,A_ORI,A_ROL,A_ROR,A_SBC,A_SBCI,A_SUB,A_SUBI]) and
+              GetNextInstruction(p, hp1) and
+              MatchInstruction(hp1, A_CP) and
+              (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
+              (taicpu(hp1).oper[1]^.reg = NR_R1) and
+              GetNextInstruction(hp1, hp2) and
+              { be careful here, following instructions could use other flags
+                however after a jump fpc never depends on the value of flags }
+              { All above instructions set Z and N according to the following
+                Z := result = 0;
+                N := result[31];
+                EQ = Z=1; NE = Z=0;
+                MI = N=1; PL = N=0; }
+              MatchInstruction(hp2, A_BRxx) and
+              (taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL]) { and
+              no flag allocation tracking implemented yet on avr
+              assigned(FindRegDealloc(NR_DEFAULTFLAGS,tai(hp2.Next)))} then
+              begin
+                { move flag allocation if possible }
+                { no flag allocation tracking implemented yet on avr
+                GetLastInstruction(hp1, hp2);
+                hp2:=FindRegAlloc(NR_DEFAULTFLAGS,tai(hp2.Next));
+                if assigned(hp2) then
+                  begin
+                    asml.Remove(hp2);
+                    asml.insertbefore(hp2, p);
+                  end;
+                }
+
+                asml.remove(hp1);
+                hp1.free;
+                Result:=true;
+              end
+            else
               case taicpu(p).opcode of
                 A_LDI:
                   begin