From b2f5f6ac7d3527806868807d95621861b3a0247d Mon Sep 17 00:00:00 2001 From: florian Date: Mon, 24 Feb 2025 23:05:49 +0100 Subject: [PATCH] + RiscV32: use sext.b if available --- compiler/riscv32/cgcpu.pas | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/riscv32/cgcpu.pas b/compiler/riscv32/cgcpu.pas index e9a0771679..f750e11ca5 100644 --- a/compiler/riscv32/cgcpu.pas +++ b/compiler/riscv32/cgcpu.pas @@ -125,6 +125,8 @@ unit cgcpu; list.concat(ai); rg[R_INTREGISTER].add_move_instruction(ai); end + else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_S8) then + list.Concat(taicpu.op_reg_reg(A_SEXT_B,reg2,reg1)) else if (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_8) then list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF)) else if (tosize=OS_8) and (fromsize<>OS_8) then