From b321f867c6c1248f235b2cfeeb5ac2bed9688210 Mon Sep 17 00:00:00 2001 From: florian Date: Sun, 10 Mar 2013 18:51:42 +0000 Subject: [PATCH] + trgintcpu.add_cpu_interferences for i8086 so references are properly build * empty make_simple_ref code path for i8086 git-svn-id: branches/i8086@23782 - --- compiler/i8086/cgcpu.pas | 2 +- compiler/i8086/rgcpu.pas | 44 ++++++++++++++++++++++++++++++++++++++-- compiler/x86/cgx86.pas | 7 ++++--- 3 files changed, 47 insertions(+), 6 deletions(-) diff --git a/compiler/i8086/cgcpu.pas b/compiler/i8086/cgcpu.pas index 4ffd673a59..e611a1345e 100644 --- a/compiler/i8086/cgcpu.pas +++ b/compiler/i8086/cgcpu.pas @@ -112,7 +112,7 @@ unit cgcpu; if (cs_useebp in current_settings.optimizerswitches) and assigned(current_procinfo) and (current_procinfo.framepointer<>NR_BP) then rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_AX,RS_DX,RS_CX,RS_BX,RS_SI,RS_DI,RS_BP],first_int_imreg,[]) else - rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_AX,RS_DX,RS_CX,RS_BX,RS_SI,RS_DI],first_int_imreg,[RS_BP]); + rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_AX,RS_DX,RS_CX,RS_BX,RS_SI,RS_DI],first_int_imreg,[RS_BP]); rg[R_MMXREGISTER]:=trgcpu.create(R_MMXREGISTER,R_SUBNONE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]); rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBWHOLE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]); rgfpu:=Trgx86fpu.create; diff --git a/compiler/i8086/rgcpu.pas b/compiler/i8086/rgcpu.pas index 8041041d52..378a1d4a85 100644 --- a/compiler/i8086/rgcpu.pas +++ b/compiler/i8086/rgcpu.pas @@ -38,11 +38,18 @@ unit rgcpu; procedure add_constraints(reg:Tregister);override; end; + trgintcpu = class(trgcpu) + procedure add_cpu_interferences(p : tai);override; + end; + + implementation uses - systems, - verbose; + systems, + verbose, + aasmcpu, + cgutils; const { This value is used in tsaved. If the array value is equal @@ -68,4 +75,37 @@ implementation end; + procedure trgintcpu.add_cpu_interferences(p : tai); + var + href : treference; + i : integer; + begin + if p.typ=ait_instruction then + begin + for i:=0 to taicpu(p).ops-1 do + begin + if taicpu(p).oper[i]^.typ=top_ref then + begin + href:=taicpu(p).oper[i]^.ref^; + if (href.base<>NR_NO) and (getsupreg(href.base)>=first_int_imreg) then + begin + add_edge(getsupreg(href.base),RS_AX); + add_edge(getsupreg(href.base),RS_CX); + add_edge(getsupreg(href.base),RS_DX); + add_edge(getsupreg(href.base),RS_SI); + add_edge(getsupreg(href.base),RS_DI); + end; + if (href.index<>NR_NO) and (getsupreg(href.index)>=first_int_imreg) then + begin + add_edge(getsupreg(href.index),RS_AX); + add_edge(getsupreg(href.index),RS_BX); + add_edge(getsupreg(href.index),RS_CX); + add_edge(getsupreg(href.index),RS_DX); + add_edge(getsupreg(href.index),RS_BP); + end; + end; + end; + end; + end; + end. diff --git a/compiler/x86/cgx86.pas b/compiler/x86/cgx86.pas index 59eb4a56b9..fb15d0b6db 100644 --- a/compiler/x86/cgx86.pas +++ b/compiler/x86/cgx86.pas @@ -375,7 +375,7 @@ unit cgx86; if (ref.refaddr in [addr_pic,addr_pic_no_got]) then exit; -{$ifdef x86_64} +{$if defined(x86_64)} { Only 32bit is allowed } { Note that this isn't entirely correct: for RIP-relative targets/memory models, it is actually (offset+@symbol-RIP) that should fit into 32 bits. Since two last @@ -511,7 +511,7 @@ unit cgx86; end; end; -{$else x86_64} +{$elseif defined(i386)} add_hreg:=false; if (target_info.system in [system_i386_darwin,system_i386_iphonesim]) then begin @@ -567,7 +567,8 @@ unit cgx86; ref.base:=hreg; end; end; -{$endif x86_64} +{$elseif defined(i8086)} +{$endif} end;