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* Xtensa: fix flag handling: B0 is considered as default flags
git-svn-id: trunk@44687 -
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75fe6c23a5
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@ -4354,7 +4354,9 @@ implementation
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LOC_FLAGS :
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begin
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a_jmp_flags(list,p.location.resflags,truelabel);
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{$ifndef xtensa}
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a_reg_dealloc(list,NR_DEFAULTFLAGS);
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{$endif xtensa}
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a_jmp_always(list,falselabel);
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end;
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{$endif cpuflags}
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@ -332,11 +332,7 @@ implementation
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LOC_FLAGS :
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begin
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cg.a_jmp_flags(list,p.location.resflags,truelabel);
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{ e.g. xtensa has no default flags but uses a boolean register }
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{$ifndef xtensa}
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cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
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{$endif xtensa}
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cg.a_jmp_always(list,falselabel);
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end;
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{$endif cpuflags}
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@ -144,6 +144,9 @@ implementation
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,
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RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15],first_fpu_imreg,[]);
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rg[R_SPECIALREGISTER]:=trgcpu.create(R_SPECIALREGISTER,R_SUBNONE,
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[RS_B0,RS_B1,RS_B2,RS_B3,RS_B4,RS_B5,RS_B6,RS_B7,RS_B8,RS_B9,
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RS_B10,RS_B11,RS_B12,RS_B13,RS_B14,RS_B15],first_flag_imreg,[]);
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end;
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@ -151,6 +154,7 @@ implementation
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begin
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rg[R_INTREGISTER].free;
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rg[R_FPUREGISTER].free;
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rg[R_SPECIALREGISTER].free;
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inherited done_register_allocators;
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end;
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@ -84,6 +84,9 @@ unit cpubase;
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first_mm_supreg = RS_INVALID;
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first_mm_imreg = $30;
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{ firs flag imaginary register }
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first_flag_imreg = $10;
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{ TODO: Calculate bsstart}
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regnumber_count_bsstart = 16;
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@ -223,8 +226,9 @@ unit cpubase;
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{ Offset where the parent framepointer is pushed }
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PARENT_FRAMEPOINTER_OFFSET = 0;
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NR_DEFAULTFLAGS = NR_INVALID;
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RS_DEFAULTFLAGS = RS_INVALID;
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{ we consider B0 as the default flag }
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NR_DEFAULTFLAGS = NR_B0;
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RS_DEFAULTFLAGS = RS_B0;
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{*****************************************************************************
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GCC /ABI linking information
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@ -283,7 +283,8 @@ interface
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{ emit the actual operation }
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if cmpop then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.getcpuregister(current_asmdata.CurrAsmList,location.resflags.register);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.resflags.register,left.location.register,right.location.register));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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if inv then
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