mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-20 19:29:26 +02:00
+ software handling of exceptions on arm
* reworked software handling of exceptions so they can be check lazily git-svn-id: trunk@42525 -
This commit is contained in:
florian
parent
847ac91d1d
commit
b3ed34592f
@ -61,6 +61,8 @@ unit cgcpu;
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procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
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procedure g_check_for_fpu_exception(list : TAsmList; force,clear : boolean); override;
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procedure a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
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{ comparison operations }
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procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
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@ -1720,6 +1722,33 @@ unit cgcpu;
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end;
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procedure tbasecgarm.g_check_for_fpu_exception(list: TAsmList;force,clear : boolean);
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var
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r : TRegister;
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ai: taicpu;
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l: TAsmLabel;
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begin
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if ((cs_check_fpu_exceptions in current_settings.localswitches) and
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(force or current_procinfo.FPUExceptionCheckNeeded)) then
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begin
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r:=getintregister(list,OS_INT);
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list.concat(taicpu.op_reg_reg(A_FMRX,r,NR_FPSCR));
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list.concat(setoppostfix(taicpu.op_reg_reg_const(A_AND,r,r,$9f),PF_S));
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current_asmdata.getjumplabel(l);
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ai:=taicpu.op_sym(A_B,l);
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ai.is_jmp:=true;
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ai.condition:=C_EQ;
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list.concat(ai);
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alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_THROWFPUEXCEPTION',false);
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dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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a_label(list,l);
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if clear then
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current_procinfo.FPUExceptionCheckNeeded:=false;
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end;
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end;
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{ comparison operations }
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procedure tbasecgarm.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
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l : tasmlabel);
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@ -3069,6 +3098,7 @@ unit cgcpu;
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else
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;
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end;
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maybe_check_for_fpu_exception(list);
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end;
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@ -3134,6 +3164,7 @@ unit cgcpu;
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if (tmpmmreg<>reg) then
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a_loadmm_reg_reg(list,fromsize,tosize,tmpmmreg,reg,shuffle);
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maybe_check_for_fpu_exception(list);
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end;
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@ -3199,6 +3230,7 @@ unit cgcpu;
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begin
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handle_load_store(list,A_VSTR,PF_None,tmpmmreg,ref);
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end;
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maybe_check_for_fpu_exception(list);
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end;
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@ -3214,6 +3246,7 @@ unit cgcpu;
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not shufflescalar(shuffle) then
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internalerror(2009112516);
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list.concat(taicpu.op_reg_reg(A_VMOV,mmreg,intreg));
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maybe_check_for_fpu_exception(list);
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end;
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@ -3229,6 +3262,7 @@ unit cgcpu;
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not shufflescalar(shuffle) then
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internalerror(2009112514);
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list.concat(taicpu.op_reg_reg(A_VMOV,intreg,mmreg));
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maybe_check_for_fpu_exception(list);
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end;
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@ -3356,6 +3390,7 @@ unit cgcpu;
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if (mmsize<>OS_F64) then
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internalerror(2009112405);
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list.concat(taicpu.op_reg_reg_reg(A_VMOV,mmreg,intreg.reglo,intreg.reghi));
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cg.maybe_check_for_fpu_exception(list);
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end;
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@ -3366,6 +3401,7 @@ unit cgcpu;
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if (mmsize<>OS_F64) then
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internalerror(2009112406);
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list.concat(taicpu.op_reg_reg_reg(A_VMOV,intreg.reglo,intreg.reghi,mmreg));
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cg.maybe_check_for_fpu_exception(list);
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end;
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@ -5196,6 +5232,7 @@ unit cgcpu;
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instr:=setoppostfix(taicpu.op_reg_reg(A_VMOV,reg2,reg1), PF_F32);
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list.Concat(instr);
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add_move_instruction(instr);
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maybe_check_for_fpu_exception(list);
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end
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else if (fromsize=OS_F64) and
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(tosize=OS_F64) then
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@ -5221,6 +5258,7 @@ unit cgcpu;
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procedure tthumb2cgarm.a_loadmm_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference; shuffle: pmmshuffle);
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begin
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handle_load_store(list,A_VSTR,PF_None,reg,ref);
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maybe_check_for_fpu_exception(list);
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end;
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@ -5238,7 +5276,10 @@ unit cgcpu;
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begin
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if //(shuffle=nil) and
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(fromsize=OS_F32) then
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list.Concat(taicpu.op_reg_reg(A_VMOV,intreg,mmreg))
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begin
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list.Concat(taicpu.op_reg_reg(A_VMOV,intreg,mmreg));
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maybe_check_for_fpu_exception(list);
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end
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else
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internalerror(2012100814);
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end;
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@ -238,6 +238,7 @@ interface
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,right.location.register),pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_fpv4_s16:
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begin
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@ -263,6 +264,7 @@ interface
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end;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op, location.register,left.location.register,right.location.register), PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_soft:
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{ this case should be handled already by pass1 }
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@ -325,6 +327,7 @@ interface
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(op,
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left.location.register,right.location.register), pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VMRS,NR_APSR_nzcv,NR_FPSCR));
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location.resflags:=GetFpuResFlags;
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@ -341,6 +344,7 @@ interface
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(op,
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left.location.register,right.location.register),PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_VMRS, NR_APSR_nzcv, NR_FPSCR));
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end;
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@ -272,9 +272,13 @@ implementation
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register),pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register), PF_F32));
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begin
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register), PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_soft:
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begin
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if singleprec then
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@ -309,9 +313,13 @@ implementation
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register),pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register), PF_F32));
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begin
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register), PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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else
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internalerror(2009111403);
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end;
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@ -339,9 +347,13 @@ implementation
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register),pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register), PF_F32));
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begin
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register), PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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else
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internalerror(2009111402);
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end;
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@ -515,6 +527,7 @@ implementation
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oppostfix:=PF_F32;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op[negproduct,negop3],
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location.register,paraarray[1].location.register,paraarray[2].location.register),oppostfix));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end
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else
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internalerror(2014032301);
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@ -435,6 +435,7 @@ implementation
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
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location.register,left.location.register), pf));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_fpv4_s16:
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begin
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@ -444,6 +445,7 @@ implementation
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
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location.register,left.location.register), PF_F32));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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fpu_soft:
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begin
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@ -453,7 +453,8 @@ unit cgobj;
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{ some CPUs do not support hardware fpu exceptions, this procedure is called after instructions which
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might set FPU exception related flags, so it has to check these flags if needed and throw an exeception }
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procedure g_check_for_fpu_exception(list: TAsmList); virtual;
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procedure g_check_for_fpu_exception(list : TAsmList; force,clear : boolean); virtual;
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procedure maybe_check_for_fpu_exception(list: TAsmList);
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protected
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function g_indirect_sym_load(list:TAsmList;const symname: string; const flags: tindsymflags): tregister;virtual;
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@ -2930,12 +2931,18 @@ implementation
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end;
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procedure tcg.g_check_for_fpu_exception(list: TAsmList);
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procedure tcg.g_check_for_fpu_exception(list: TAsmList;force,clear : boolean);
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begin
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{ empty by default }
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end;
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procedure tcg.maybe_check_for_fpu_exception(list: TAsmList);
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begin
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current_procinfo.FPUExceptionCheckNeeded:=true;
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g_check_for_fpu_exception(list,false,true);
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end;
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{*****************************************************************************
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TCG64
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*****************************************************************************}
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@ -1280,7 +1280,7 @@ implementation
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{ check for fpu exceptions }
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if cnf_check_fpu_exceptions in callnodeflags then
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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{ perhaps i/o check ? }
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if (cs_check_io in current_settings.localswitches) and
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@ -136,6 +136,10 @@ unit procinfo;
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Requires different entry code for some targets. }
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ConstructorCallingConstructor: boolean;
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{ true, if an FPU instruction has been generated which could raise an exception and where the flags
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need to be checked explicitly like on RISC-V or certain ARM architectures }
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FPUExceptionCheckNeeded : Boolean;
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constructor create(aparent:tprocinfo);virtual;
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destructor destroy;override;
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@ -72,7 +72,7 @@ unit cgrv;
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procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
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procedure g_check_for_fpu_exception(list: TAsmList); override;
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procedure g_check_for_fpu_exception(list: TAsmList;force,clear : boolean); override;
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protected
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function fixref(list: TAsmList; var ref: treference): boolean;
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procedure maybeadjustresult(list: TAsmList; op: topcg; size: tcgsize; dst: tregister);
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@ -614,7 +614,7 @@ unit cgrv;
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if fromsize<>tosize then
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begin
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list.concat(taicpu.op_reg_reg(convOp[fromsize,tosize],reg2,reg1));
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g_check_for_fpu_exception(list);
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maybe_check_for_fpu_exception(list);
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end
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else
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begin
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@ -786,7 +786,7 @@ unit cgrv;
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end;
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procedure tcgrv.g_check_for_fpu_exception(list: TAsmList);
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procedure tcgrv.g_check_for_fpu_exception(list: TAsmList;force,clear : boolean);
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var
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r : TRegister;
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ai: taicpu;
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@ -423,12 +423,12 @@ implementation
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if not cmpop then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end
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else
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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if inv then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_XORI,location.register,location.register,1));
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@ -160,13 +160,13 @@ implementation
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FSQRT_S,location.register,
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left.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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OS_F64:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FSQRT_D,location.register,
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left.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end
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else
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inherited;
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@ -199,7 +199,7 @@ implementation
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else
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op := A_FMUL_D;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,left.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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@ -237,7 +237,7 @@ implementation
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{$endif}
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,left.location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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@ -275,7 +275,7 @@ implementation
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{$endif}
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_roundingmode(op,location.register,left.location.register,RM_RTZ));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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@ -349,7 +349,7 @@ implementation
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(op[def_cgsize(resultdef), negproduct,negop3],location.register,paraarray[1].location.register,paraarray[2].location.register,paraarray[2].location.register));
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cg.g_check_for_fpu_exception(current_asmdata.CurrAsmList);
|
||||
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
|
||||
end
|
||||
else
|
||||
internalerror(2014032301);
|
||||
|
||||
@ -47,6 +47,63 @@ begin
|
||||
end;
|
||||
end;
|
||||
{$else}
|
||||
|
||||
|
||||
const
|
||||
fpu_nx = 1 shl 0;
|
||||
fpu_uf = 1 shl 1;
|
||||
fpu_of = 1 shl 2;
|
||||
fpu_dz = 1 shl 3;
|
||||
fpu_nv = 1 shl 4;
|
||||
|
||||
function getfpscr: sizeuint; nostackframe; assembler;
|
||||
asm
|
||||
fmrx r0,fpscr
|
||||
end;
|
||||
|
||||
|
||||
procedure setfpscr(flags : sizeuint); nostackframe; assembler;
|
||||
asm
|
||||
fmxr fpscr,r0
|
||||
end;
|
||||
|
||||
|
||||
const
|
||||
FPSCR_IOC = 1;
|
||||
FPSCR_DZC = 1 shl 1;
|
||||
FPSCR_OFC = 1 shl 2;
|
||||
FPSCR_UFC = 1 shl 3;
|
||||
FPSCR_IXC = 1 shl 4;
|
||||
FPSCR_IDC = 1 shl 7;
|
||||
|
||||
|
||||
procedure fpc_throwfpuexception;[public,alias:'FPC_THROWFPUEXCEPTION'];
|
||||
var
|
||||
fpscr : longint;
|
||||
f: TFPUException;
|
||||
begin
|
||||
{ at this point, we know already, that an exception will be risen }
|
||||
fpscr:=getfpscr;
|
||||
|
||||
if (fpscr and FPSCR_DZC) <> 0 then
|
||||
float_raise(exZeroDivide);
|
||||
if (fpscr and FPSCR_OFC) <> 0 then
|
||||
float_raise(exOverflow);
|
||||
if (fpscr and FPSCR_UFC) <> 0 then
|
||||
float_raise(exUnderflow);
|
||||
if (fpscr and FPSCR_IOC) <> 0 then
|
||||
float_raise(exInvalidOp);
|
||||
if (fpscr and FPSCR_IXC) <> 0 then
|
||||
float_raise(exPrecision);
|
||||
if (fpscr and FPSCR_IDC) <> 0 then
|
||||
float_raise(exDenormalized);
|
||||
|
||||
{ now the soft float exceptions }
|
||||
for f in softfloat_exception_flags do
|
||||
float_raise(f);
|
||||
end;
|
||||
|
||||
|
||||
Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
|
||||
begin
|
||||
{ Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user