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* offset of vstr/vld is limited to +/- 1020, take care of this during spilling

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git-svn-id: trunk@35396 -
This commit is contained in:
florian 2017-02-04 18:42:02 +00:00
parent f0ebae94a7
commit b41989adfa
1 changed files with 6 additions and 5 deletions
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11
compiler/arm/rgcpu.pas
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@ -188,7 +188,7 @@ unit rgcpu;
{ Lets remove the bits we can fold in later and check if the result can be easily with an add or sub }
a:=abs(spilltemp.offset);
if GenerateThumbCode then
if GenerateThumbCode or (getregtype(tempreg)=R_MMREGISTER) then
begin
{$ifdef DEBUG_SPILLING}
helplist.concat(tai_comment.create(strpnew('Spilling: Use a_load_const_reg to fix spill offset')));
@ -242,9 +242,10 @@ unit rgcpu;
end;
function fix_spilling_offset(offset : ASizeInt) : boolean;
function fix_spilling_offset(regtype : TRegisterType;offset : ASizeInt) : boolean;
begin
result:=(abs(offset)>4095) or
((regtype=R_MMREGISTER) and (abs(offset)>1020)) or
((GenerateThumbCode) and ((offset<0) or (offset>1020)));
end;
@ -254,7 +255,7 @@ unit rgcpu;
{ don't load spilled register between
mov lr,pc
mov pc,r4
but befure the mov lr,pc
but before the mov lr,pc
}
if assigned(pos.previous) and
(pos.typ=ait_instruction) and
@ -265,7 +266,7 @@ unit rgcpu;
(taicpu(pos).oper[1]^.reg=NR_PC) then
pos:=tai(pos.previous);
if fix_spilling_offset(spilltemp.offset) then
if fix_spilling_offset(getregtype(tempreg),spilltemp.offset) then
spilling_create_load_store(list, pos, spilltemp, tempreg, false)
else
inherited;
@ -274,7 +275,7 @@ unit rgcpu;
procedure trgcpu.do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister);
begin
if fix_spilling_offset(spilltemp.offset) then
if fix_spilling_offset(getregtype(tempreg),spilltemp.offset) then
spilling_create_load_store(list, pos, spilltemp, tempreg, true)
else
inherited;