mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-08-10 06:05:57 +02:00
Improved ADD and SUB optimisations for LEA instructions
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
fa4e528576
commit
b58fdc3e58
@ -365,6 +365,9 @@ unit aoptcpu;
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Result:=PostPeepholeOptMOVSX(p);
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A_SHR:
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Result:=PostPeepholeOptShr(p);
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A_ADD,
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A_SUB:
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Result:=PostPeepholeOptADDSUB(p);
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A_VPXOR:
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Result:=PostPeepholeOptVPXOR(p);
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else
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@ -188,6 +188,7 @@ unit aoptx86;
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function PostPeepholeOptLea(var p : tai) : Boolean;
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function PostPeepholeOptPush(var p: tai): Boolean;
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function PostPeepholeOptShr(var p : tai) : boolean;
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function PostPeepholeOptADDSUB(var p : tai) : Boolean;
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function PostPeepholeOptVPXOR(var p: tai): Boolean;
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procedure ConvertJumpToRET(const p: tai; const ret_p: tai);
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@ -4260,9 +4261,21 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass1Add(var p : tai) : boolean;
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var
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hp1 : tai;
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hp1, hp2: tai;
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ActiveReg: TRegister;
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OldOffset: asizeint;
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ThisConst: TCGInt;
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function RegDeallocated: Boolean;
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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Result := not(RegUsedAfterInstruction(ActiveReg,hp1,TmpUsedRegs))
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end;
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begin
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result:=false;
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hp1 := nil;
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{ replace
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addX const,%reg1
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leaX (%reg1,%reg1,Y),%reg2 // Base or index might not be equal to reg1
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@ -4272,23 +4285,130 @@ unit aoptx86;
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leaX const+const*Y(%reg1,%reg1,Y),%reg2
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}
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if MatchOpType(taicpu(p),top_const,top_reg) and
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GetNextInstruction(p,hp1) and
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MatchInstruction(hp1,A_LEA,[taicpu(p).opsize]) and
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((taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.base) or
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(taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.index)) then
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if MatchOpType(taicpu(p),top_const,top_reg) then
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
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ActiveReg := taicpu(p).oper[1]^.reg;
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{ Ensures the entire register was updated }
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if (taicpu(p).opsize >= S_L) and
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GetNextInstructionUsingReg(p,hp1, ActiveReg) and
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MatchInstruction(hp1,A_LEA,[]) and
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(SuperRegistersEqual(ActiveReg, taicpu(hp1).oper[0]^.ref^.base) or
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SuperRegistersEqual(ActiveReg, taicpu(hp1).oper[0]^.ref^.index)) and
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(
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{ Cover the case where the register in the reference is also the destination register }
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Reg1WriteOverwritesReg2Entirely(taicpu(hp1).oper[1]^.reg, ActiveReg) or
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(
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{ Try to avoid the expensive check of RegUsedAfterInstruction if we know it will return False }
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not SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, ActiveReg) and
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RegDeallocated
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)
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) then
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begin
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DebugMsg(SPeepholeOptimization + 'AddLea2Lea done',p);
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if taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.base then
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OldOffset := taicpu(hp1).oper[0]^.ref^.offset;
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if ActiveReg=taicpu(hp1).oper[0]^.ref^.base then
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inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val);
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if taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.index then
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if ActiveReg=taicpu(hp1).oper[0]^.ref^.index then
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inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val*max(taicpu(hp1).oper[0]^.ref^.scalefactor,1));
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RemoveCurrentP(p);
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result:=true;
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if (taicpu(hp1).oper[0]^.ref^.offset > $7FFFFFFF) or (taicpu(hp1).oper[0]^.ref^.offset < -2147483648) then
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begin
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{ Overflow; abort }
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taicpu(hp1).oper[0]^.ref^.offset := OldOffset;
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end
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else
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begin
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DebugMsg(SPeepholeOptimization + 'AddLea2Lea done',p);
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if not (cs_opt_level3 in current_settings.optimizerswitches) then
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{ hp1 is the immediate next instruction for sure - good for a quick speed boost }
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RemoveCurrentP(p, hp1)
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else
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RemoveCurrentP(p);
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result:=true;
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Exit;
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end;
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end;
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if (
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{ Save calling GetNextInstructionUsingReg again }
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Assigned(hp1) or
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GetNextInstructionUsingReg(p,hp1, ActiveReg)
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) and
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MatchInstruction(hp1,A_ADD,A_SUB,[taicpu(p).opsize]) and
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(taicpu(hp1).oper[1]^.reg = ActiveReg) then
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begin
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if taicpu(hp1).oper[0]^.typ = top_const then
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begin
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{ Merge add const1,%reg; add/sub const2,%reg to add const1+/-const2,%reg }
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if taicpu(hp1).opcode = A_ADD then
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ThisConst := taicpu(p).oper[0]^.val + taicpu(hp1).oper[0]^.val
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else
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ThisConst := taicpu(p).oper[0]^.val - taicpu(hp1).oper[0]^.val;
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Result := True;
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{ Handle any overflows }
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case taicpu(p).opsize of
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S_B:
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taicpu(p).oper[0]^.val := ThisConst and $FF;
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S_W:
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taicpu(p).oper[0]^.val := ThisConst and $FFFF;
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S_L:
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taicpu(p).oper[0]^.val := ThisConst and $FFFFFFFF;
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{$ifdef x86_64}
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S_Q:
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if (ThisConst > $7FFFFFFF) or (ThisConst < -2147483648) then
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{ Overflow; abort }
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Result := False
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else
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taicpu(p).oper[0]^.val := ThisConst;
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{$endif x86_64}
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else
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InternalError(2021102610);
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end;
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{ Result may get set to False again if the combined immediate overflows for S_Q sizes }
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if Result then
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begin
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if (taicpu(p).oper[0]^.val < 0) and
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(
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((taicpu(p).opsize = S_B) and (taicpu(p).oper[0]^.val <> -128)) or
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((taicpu(p).opsize = S_W) and (taicpu(p).oper[0]^.val <> -32768)) or
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((taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif x86_64}]) and (taicpu(p).oper[0]^.val <> -2147483648))
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) then
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begin
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DebugMsg(SPeepholeOptimization + 'ADD; ADD/SUB -> SUB',p);
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taicpu(p).opcode := A_SUB;
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taicpu(p).oper[0]^.val := -taicpu(p).oper[0]^.val;
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end
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else
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DebugMsg(SPeepholeOptimization + 'ADD; ADD/SUB -> ADD',p);
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RemoveInstruction(hp1);
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end;
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end
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else
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begin
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{ Make doubly sure the flags aren't in use because the order of additions may affect them }
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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hp2 := p;
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while not (cs_opt_level3 in current_settings.optimizerswitches) and
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GetNextInstruction(hp2, hp2) and (hp2 <> hp1) do
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.next));
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if not RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) then
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begin
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{ Move the constant addition to after the reg/ref addition to improve optimisation }
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DebugMsg(SPeepholeOptimization + 'Add/sub swap 1a done',p);
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Asml.Remove(p);
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Asml.InsertAfter(p, hp1);
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p := hp1;
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Result := True;
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end;
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end;
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end;
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end;
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end;
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@ -4720,19 +4840,23 @@ unit aoptx86;
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hp1 : tai;
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begin
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DoSubAddOpt := False;
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if taicpu(p).oper[0]^.typ <> top_const then
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{ Should have been confirmed before calling }
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InternalError(2021102601);
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if GetLastInstruction(p, hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opsize = taicpu(p).opsize) then
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case taicpu(hp1).opcode Of
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A_DEC:
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if (taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
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if MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
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begin
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taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+1);
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RemoveInstruction(hp1);
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end;
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A_SUB:
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if MatchOpType(taicpu(hp1),top_const,top_reg) and
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if (taicpu(hp1).oper[0]^.typ = top_const) and
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MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
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begin
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taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
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@ -4740,7 +4864,7 @@ unit aoptx86;
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end;
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A_ADD:
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begin
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if MatchOpType(taicpu(hp1),top_const,top_reg) and
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if (taicpu(hp1).oper[0]^.typ = top_const) and
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MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
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begin
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taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
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@ -4762,20 +4886,160 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass1Sub(var p : tai) : boolean;
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{$ifdef i386}
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var
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hp1 : tai;
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{$endif i386}
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hp1, hp2: tai;
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ActiveReg: TRegister;
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OldOffset: asizeint;
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ThisConst: TCGInt;
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function RegDeallocated: Boolean;
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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Result := not(RegUsedAfterInstruction(ActiveReg,hp1,TmpUsedRegs))
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end;
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begin
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Result:=false;
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hp1 := nil;
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{ replace
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subX const,%reg1
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leaX (%reg1,%reg1,Y),%reg2 // Base or index might not be equal to reg1
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dealloc %reg1
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by
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leaX -const-const*Y(%reg1,%reg1,Y),%reg2
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}
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if MatchOpType(taicpu(p),top_const,top_reg) then
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begin
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ActiveReg := taicpu(p).oper[1]^.reg;
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{ Ensures the entire register was updated }
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if (taicpu(p).opsize >= S_L) and
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GetNextInstructionUsingReg(p,hp1, ActiveReg) and
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MatchInstruction(hp1,A_LEA,[]) and
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(SuperRegistersEqual(ActiveReg, taicpu(hp1).oper[0]^.ref^.base) or
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SuperRegistersEqual(ActiveReg, taicpu(hp1).oper[0]^.ref^.index)) and
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(
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{ Cover the case where the register in the reference is also the destination register }
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Reg1WriteOverwritesReg2Entirely(taicpu(hp1).oper[1]^.reg, ActiveReg) or
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(
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{ Try to avoid the expensive check of RegUsedAfterInstruction if we know it will return False }
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not SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, ActiveReg) and
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RegDeallocated
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)
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) then
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begin
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OldOffset := taicpu(hp1).oper[0]^.ref^.offset;
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if ActiveReg=taicpu(hp1).oper[0]^.ref^.base then
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Dec(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val);
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if ActiveReg=taicpu(hp1).oper[0]^.ref^.index then
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Dec(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val*max(taicpu(hp1).oper[0]^.ref^.scalefactor,1));
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if (taicpu(hp1).oper[0]^.ref^.offset > $7FFFFFFF) or (taicpu(hp1).oper[0]^.ref^.offset < -2147483648) then
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begin
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{ Overflow; abort }
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taicpu(hp1).oper[0]^.ref^.offset := OldOffset;
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end
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else
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begin
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DebugMsg(SPeepholeOptimization + 'SubLea2Lea done',p);
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if not (cs_opt_level3 in current_settings.optimizerswitches) then
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{ hp1 is the immediate next instruction for sure - good for a quick speed boost }
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RemoveCurrentP(p, hp1)
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else
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RemoveCurrentP(p);
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result:=true;
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Exit;
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end;
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end;
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if (
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{ Save calling GetNextInstructionUsingReg again }
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Assigned(hp1) or
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GetNextInstructionUsingReg(p,hp1, ActiveReg)
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) and
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MatchInstruction(hp1,A_SUB,[taicpu(p).opsize]) and
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(taicpu(hp1).oper[1]^.reg = ActiveReg) then
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begin
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if taicpu(hp1).oper[0]^.typ = top_const then
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begin
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{ Merge add const1,%reg; add const2,%reg to add const1+const2,%reg }
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ThisConst := taicpu(p).oper[0]^.val + taicpu(hp1).oper[0]^.val;
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Result := True;
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{ Handle any overflows }
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case taicpu(p).opsize of
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S_B:
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taicpu(p).oper[0]^.val := ThisConst and $FF;
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S_W:
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taicpu(p).oper[0]^.val := ThisConst and $FFFF;
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S_L:
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taicpu(p).oper[0]^.val := ThisConst and $FFFFFFFF;
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{$ifdef x86_64}
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S_Q:
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if (ThisConst > $7FFFFFFF) or (ThisConst < -2147483648) then
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{ Overflow; abort }
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Result := False
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else
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taicpu(p).oper[0]^.val := ThisConst;
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{$endif x86_64}
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else
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InternalError(2021102610);
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end;
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{ Result may get set to False again if the combined immediate overflows for S_Q sizes }
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if Result then
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begin
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if (taicpu(p).oper[0]^.val < 0) and
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(
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((taicpu(p).opsize = S_B) and (taicpu(p).oper[0]^.val <> -128)) or
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((taicpu(p).opsize = S_W) and (taicpu(p).oper[0]^.val <> -32768)) or
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((taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif x86_64}]) and (taicpu(p).oper[0]^.val <> -2147483648))
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) then
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begin
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DebugMsg(SPeepholeOptimization + 'SUB; ADD/SUB -> ADD',p);
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taicpu(p).opcode := A_SUB;
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taicpu(p).oper[0]^.val := -taicpu(p).oper[0]^.val;
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end
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else
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DebugMsg(SPeepholeOptimization + 'SUB; ADD/SUB -> SUB',p);
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RemoveInstruction(hp1);
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end;
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end
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else
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begin
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{ Make doubly sure the flags aren't in use because the order of subtractions may affect them }
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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hp2 := p;
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while not (cs_opt_level3 in current_settings.optimizerswitches) and
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GetNextInstruction(hp2, hp2) and (hp2 <> hp1) do
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.next));
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if not RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) then
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begin
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{ Move the constant subtraction to after the reg/ref addition to improve optimisation }
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DebugMsg(SPeepholeOptimization + 'Add/sub swap 1b done',p);
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Asml.Remove(p);
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Asml.InsertAfter(p, hp1);
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p := hp1;
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Result := True;
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Exit;
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end;
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end;
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end;
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{ * change "subl $2, %esp; pushw x" to "pushl x"}
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{ * change "sub/add const1, reg" or "dec reg" followed by
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"sub const2, reg" to one "sub ..., reg" }
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if MatchOpType(taicpu(p),top_const,top_reg) then
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begin
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{$ifdef i386}
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if (taicpu(p).oper[0]^.val = 2) and
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(taicpu(p).oper[1]^.reg = NR_ESP) and
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(ActiveReg = NR_ESP) and
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{ Don't do the sub/push optimization if the sub }
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{ comes from setting up the stack frame (JM) }
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(not(GetLastInstruction(p,hp1)) or
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@ -6635,6 +6899,46 @@ unit aoptx86;
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NewInstr : Taicpu;
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NewAligh : Tai_align;
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DestLabel: TAsmLabel;
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function TryMovArith2Lea(InputInstr: tai): Boolean;
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var
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NextInstr: tai;
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begin
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Result := False;
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UpdateUsedRegs(TmpUsedRegs, tai(InputInstr.Next));
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if not GetNextInstruction(InputInstr, NextInstr) or
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(
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{ The FLAGS register isn't always tracked properly, so do not
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perform this optimisation if a conditional statement follows }
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not RegReadByInstruction(NR_DEFAULTFLAGS, NextInstr) and
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not RegUsedAfterInstruction(NR_DEFAULTFLAGS, NextInstr, TmpUsedRegs)
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) then
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begin
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reference_reset(NewRef, 1, []);
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NewRef.base := taicpu(p).oper[0]^.reg;
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NewRef.scalefactor := 1;
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|
||||
if taicpu(InputInstr).opcode = A_ADD then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'MovAdd2Lea', p);
|
||||
NewRef.offset := taicpu(InputInstr).oper[0]^.val;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'MovSub2Lea', p);
|
||||
NewRef.offset := -taicpu(InputInstr).oper[0]^.val;
|
||||
end;
|
||||
|
||||
taicpu(p).opcode := A_LEA;
|
||||
taicpu(p).loadref(0, NewRef);
|
||||
|
||||
RemoveInstruction(InputInstr);
|
||||
|
||||
Result := True;
|
||||
end;
|
||||
end;
|
||||
|
||||
begin
|
||||
Result:=false;
|
||||
|
||||
@ -6801,10 +7105,8 @@ unit aoptx86;
|
||||
else if MatchOpType(taicpu(p),top_reg,top_reg) and
|
||||
(taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif x86_64}]) and
|
||||
MatchInstruction(hp1,A_ADD,A_SUB,[taicpu(p).opsize]) and
|
||||
MatchOpType(taicpu(hp1),top_const,top_reg) and
|
||||
(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) and
|
||||
{ be lazy, checking separately for sub would be slightly better }
|
||||
(abs(taicpu(hp1).oper[0]^.val)<=$7fffffff) then
|
||||
(taicpu(hp1).oper[1]^.typ = top_reg) and
|
||||
(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
|
||||
begin
|
||||
{ Change:
|
||||
movl/q %reg1,%reg2 movl/q %reg1,%reg2
|
||||
@ -6812,39 +7114,36 @@ unit aoptx86;
|
||||
To:
|
||||
leal/q x(%reg1),%reg2 leal/q -x(%reg1),%reg2
|
||||
}
|
||||
TransferUsedRegs(TmpUsedRegs);
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
|
||||
if not GetNextInstruction(hp1, hp2) or
|
||||
(
|
||||
{ The FLAGS register isn't always tracked properly, so do not
|
||||
perform this optimisation if a conditional statement follows }
|
||||
not RegReadByInstruction(NR_DEFAULTFLAGS, hp2) and
|
||||
not RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp2, TmpUsedRegs)
|
||||
) then
|
||||
if (taicpu(hp1).oper[0]^.typ = top_const) and
|
||||
{ be lazy, checking separately for sub would be slightly better }
|
||||
(abs(taicpu(hp1).oper[0]^.val)<=$7fffffff) then
|
||||
begin
|
||||
reference_reset(NewRef, 1, []);
|
||||
NewRef.base := taicpu(p).oper[0]^.reg;
|
||||
NewRef.scalefactor := 1;
|
||||
|
||||
if taicpu(hp1).opcode = A_ADD then
|
||||
TransferUsedRegs(TmpUsedRegs);
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
||||
if TryMovArith2Lea(hp1) then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'MovAdd2Lea', p);
|
||||
NewRef.offset := taicpu(hp1).oper[0]^.val;
|
||||
Result := True;
|
||||
Exit;
|
||||
end
|
||||
else
|
||||
end
|
||||
else if not RegInOp(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[0]^) and
|
||||
GetNextInstructionUsingReg(hp1, hp2, taicpu(p).oper[1]^.reg) and
|
||||
{ Same as above, but also adds or subtracts to %reg2 in between.
|
||||
It's still valid as long as the flags aren't in use }
|
||||
MatchInstruction(hp2,A_ADD,A_SUB,[taicpu(p).opsize]) and
|
||||
MatchOpType(taicpu(hp2), top_const, top_reg) and
|
||||
(taicpu(hp2).oper[1]^.reg = taicpu(p).oper[1]^.reg) and
|
||||
{ be lazy, checking separately for sub would be slightly better }
|
||||
(abs(taicpu(hp2).oper[0]^.val)<=$7fffffff) then
|
||||
begin
|
||||
TransferUsedRegs(TmpUsedRegs);
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
|
||||
if TryMovArith2Lea(hp2) then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'MovSub2Lea', p);
|
||||
NewRef.offset := -taicpu(hp1).oper[0]^.val;
|
||||
Result := True;
|
||||
Exit;
|
||||
end;
|
||||
|
||||
taicpu(p).opcode := A_LEA;
|
||||
taicpu(p).loadref(0, NewRef);
|
||||
|
||||
RemoveInstruction(hp1);
|
||||
|
||||
Result := True;
|
||||
Exit;
|
||||
end;
|
||||
end
|
||||
else if MatchOpType(taicpu(p),top_reg,top_reg) and
|
||||
@ -9870,10 +10169,12 @@ unit aoptx86;
|
||||
function TX86AsmOptimizer.OptPass2Lea(var p : tai) : Boolean;
|
||||
begin
|
||||
Result:=false;
|
||||
if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
|
||||
if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) and
|
||||
(taicpu(p).oper[0]^.ref^.offset = 0) then
|
||||
begin
|
||||
if MatchReference(taicpu(p).oper[0]^.ref^,taicpu(p).oper[1]^.reg,NR_INVALID) and
|
||||
(taicpu(p).oper[0]^.ref^.index<>NR_NO) then
|
||||
if (taicpu(p).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
|
||||
(taicpu(p).oper[0]^.ref^.index <> NR_NO) and
|
||||
(taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) then
|
||||
begin
|
||||
taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.base);
|
||||
taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.index);
|
||||
@ -9882,14 +10183,29 @@ unit aoptx86;
|
||||
result:=true;
|
||||
end
|
||||
|
||||
else if MatchReference(taicpu(p).oper[0]^.ref^,NR_INVALID,taicpu(p).oper[1]^.reg) and
|
||||
(taicpu(p).oper[0]^.ref^.base<>NR_NO) then
|
||||
else if (taicpu(p).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) then
|
||||
begin
|
||||
taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.index);
|
||||
taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.base);
|
||||
taicpu(p).opcode:=A_ADD;
|
||||
DebugMsg(SPeepholeOptimization + 'Lea2AddIndex done',p);
|
||||
result:=true;
|
||||
if (taicpu(p).oper[0]^.ref^.base <> NR_NO) then
|
||||
begin
|
||||
if (taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) then
|
||||
begin
|
||||
taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.index);
|
||||
taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.base);
|
||||
taicpu(p).opcode:=A_ADD;
|
||||
DebugMsg(SPeepholeOptimization + 'Lea2AddIndex done',p);
|
||||
result:=true;
|
||||
end;
|
||||
end
|
||||
else
|
||||
if (taicpu(p).oper[0]^.ref^.scalefactor in [2, 4, 8]) then
|
||||
begin
|
||||
{ BsrByte is, in essence, the base-2 logarithm of the scale factor }
|
||||
taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.index);
|
||||
taicpu(p).loadconst(0, BsrByte(taicpu(p).oper[0]^.ref^.scalefactor));
|
||||
taicpu(p).opcode:=A_SHL;
|
||||
DebugMsg(SPeepholeOptimization + 'Lea2Shl done',p);
|
||||
result:=true;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
@ -10304,6 +10620,61 @@ unit aoptx86;
|
||||
end;
|
||||
|
||||
|
||||
function TX86AsmOptimizer.PostPeepholeOptADDSUB(var p : tai) : boolean;
|
||||
var
|
||||
hp1, hp2: tai;
|
||||
begin
|
||||
{ Detect:
|
||||
add/sub %reg2,(dest)
|
||||
add/sub x, (dest)
|
||||
|
||||
(dest can be a register or a reference)
|
||||
|
||||
Swap the instructions to minimise a pipeline stall. This reverses the
|
||||
"Add swap" and "Sub swap" optimisations done in pass 1 if no new
|
||||
optimisations could be made.
|
||||
}
|
||||
|
||||
Result := False;
|
||||
if (taicpu(p).oper[0]^.typ = top_reg) and
|
||||
not RegInOp(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^) and
|
||||
(
|
||||
(
|
||||
(taicpu(p).oper[1]^.typ = top_reg) and
|
||||
{ We can try searching further ahead if we're writing to a register }
|
||||
GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[1]^.reg)
|
||||
) or
|
||||
(
|
||||
(taicpu(p).oper[1]^.typ = top_ref) and
|
||||
GetNextInstruction(p, hp1)
|
||||
)
|
||||
) and
|
||||
MatchInstruction(hp1, A_ADD, A_SUB, [taicpu(p).opsize]) and
|
||||
(taicpu(hp1).oper[0]^.typ = top_const) and
|
||||
MatchOperand(taicpu(p).oper[1]^, taicpu(hp1).oper[1]^) then
|
||||
begin
|
||||
{ Make doubly sure the flags aren't in use because the order of additions may affect them }
|
||||
TransferUsedRegs(TmpUsedRegs);
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(p.next));
|
||||
hp2 := p;
|
||||
|
||||
while not (cs_opt_level3 in current_settings.optimizerswitches) and
|
||||
GetNextInstruction(hp2, hp2) and (hp2 <> hp1) do
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(hp2.next));
|
||||
|
||||
if not RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) then
|
||||
begin
|
||||
asml.remove(hp1);
|
||||
asml.InsertBefore(hp1, p);
|
||||
|
||||
DebugMsg(SPeepholeOptimization + 'Add/Sub swap 2 done', hp1);
|
||||
Result := True;
|
||||
end;
|
||||
end;
|
||||
|
||||
end;
|
||||
|
||||
|
||||
function TX86AsmOptimizer.PostPeepholeOptCmp(var p : tai) : Boolean;
|
||||
begin
|
||||
Result:=false;
|
||||
|
||||
@ -234,6 +234,9 @@ uses
|
||||
Result:=PostPeepholeOptPush(p);
|
||||
A_SHR:
|
||||
Result:=PostPeepholeOptShr(p);
|
||||
A_ADD,
|
||||
A_SUB:
|
||||
Result:=PostPeepholeOptADDSUB(p);
|
||||
A_VPXOR:
|
||||
Result:=PostPeepholeOptVPXOR(p);
|
||||
else
|
||||
|
||||
Loading…
Reference in New Issue
Block a user