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* Moved x86_64 mod/div code to x86, with minimal changes to ensure it compiles on i386/i8086. Merging optimized division-by-const code from i386 is pending...
git-svn-id: trunk@27930 -
This commit is contained in:
sergei
parent
0cb1a129b3
commit
b594eee70b
@ -44,11 +44,15 @@ interface
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{$endif SUPPORT_MMX}
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{$endif SUPPORT_MMX}
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end;
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end;
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tx86moddivnode = class(tcgmoddivnode)
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procedure pass_generate_code;override;
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end;
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implementation
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implementation
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uses
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uses
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globtype,
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globtype,
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systems,
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systems,constexp,
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cutils,verbose,globals,
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cutils,verbose,globals,
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symconst,symdef,
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symconst,symdef,
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aasmbase,aasmtai,aasmdata,defutil,
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aasmbase,aasmtai,aasmdata,defutil,
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@ -360,4 +364,114 @@ interface
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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end;
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end;
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{$endif SUPPORT_MMX}
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{$endif SUPPORT_MMX}
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{*****************************************************************************
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TX86MODDIVNODE
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*****************************************************************************}
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procedure tx86moddivnode.pass_generate_code;
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var
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hreg1,hreg2,rega,regd:Tregister;
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power:longint;
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op:Tasmop;
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cgsize:TCgSize;
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opsize:topsize;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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{ put numerator in register }
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cgsize:=def_cgsize(resultdef);
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opsize:=TCGSize2OpSize[cgsize];
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if not (cgsize in [OS_32,OS_S32,OS_64,OS_S64]) then
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InternalError(2013102702);
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rega:=newreg(R_INTREGISTER,RS_EAX,cgsize2subreg(R_INTREGISTER,cgsize));
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regd:=newreg(R_INTREGISTER,RS_EDX,cgsize2subreg(R_INTREGISTER,cgsize));
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location_reset(location,LOC_REGISTER,cgsize);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(int64(tordconstnode(right).value),power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resultdef) Then
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begin
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,opsize,63,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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{ (don't use emit_const_reg, because if value>high(longint)
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then it must first be loaded into a register) }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
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{ do the shift }
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emit_const_reg(A_SAR,opsize,power,hreg1);
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end
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else
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emit_const_reg(A_SHR,opsize,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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{Bring denominator to a register.}
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cg.getcpuregister(current_asmdata.CurrAsmList,rega);
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emit_reg_reg(A_MOV,opsize,hreg1,rega);
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cg.getcpuregister(current_asmdata.CurrAsmList,regd);
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{Sign extension depends on the left type.}
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if is_signed(left.resultdef) then
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case left.resultdef.size of
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{$ifdef x86_64}
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8:
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emit_none(A_CQO,S_NO);
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{$endif x86_64}
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4:
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emit_none(A_CDQ,S_NO);
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else
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internalerror(2013102701);
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end
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else
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emit_reg_reg(A_XOR,opsize,regd,regd);
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{Division depends on the right type.}
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if is_signed(right.resultdef) then
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op:=A_IDIV
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else
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op:=A_DIV;
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,opsize,right.location.reference)
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else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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emit_reg(op,opsize,right.location.register)
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else
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
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emit_reg(op,opsize,hreg1);
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end;
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{ Copy the result into a new register. Release R/EAX & R/EDX.}
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cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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if nodetype=divn then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
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else
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
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end;
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end;
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end.
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end.
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@ -29,10 +29,6 @@ interface
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node,nmat,ncgmat,nx86mat;
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node,nmat,ncgmat,nx86mat;
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type
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type
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tx8664moddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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end;
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tx8664shlshrnode = class(tshlshrnode)
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tx8664shlshrnode = class(tshlshrnode)
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procedure pass_generate_code;override;
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procedure pass_generate_code;override;
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end;
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end;
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@ -55,122 +51,6 @@ implementation
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cgbase,cgutils,cga,cgobj,hlcgobj,cgx86,
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cgbase,cgutils,cga,cgobj,hlcgobj,cgx86,
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ncgutil;
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ncgutil;
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{*****************************************************************************
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TX8664MODDIVNODE
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*****************************************************************************}
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procedure tx8664moddivnode.pass_generate_code;
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var
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hreg1,hreg2,rega,regd:Tregister;
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power:longint;
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op:Tasmop;
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cgsize:TCgSize;
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opsize:topsize;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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{ put numerator in register }
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cgsize:=def_cgsize(resultdef);
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opsize:=TCGSize2OpSize[cgsize];
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case cgsize of
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OS_S64,OS_64:
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begin
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rega:=NR_RAX;
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regd:=NR_RDX;
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end;
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OS_S32,OS_32:
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begin
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rega:=NR_EAX;
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regd:=NR_EDX;
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end;
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else
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internalerror(2013102702);
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end;
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location_reset(location,LOC_REGISTER,cgsize);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(int64(tordconstnode(right).value),power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resultdef) Then
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begin
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,opsize,63,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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{ (don't use emit_const_reg, because if value>high(longint)
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then it must first be loaded into a register) }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
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{ do the shift }
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emit_const_reg(A_SAR,opsize,power,hreg1);
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end
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else
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emit_const_reg(A_SHR,opsize,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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{Bring denominator to a register.}
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cg.getcpuregister(current_asmdata.CurrAsmList,rega);
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emit_reg_reg(A_MOV,opsize,hreg1,rega);
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cg.getcpuregister(current_asmdata.CurrAsmList,regd);
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{Sign extension depends on the left type.}
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if is_signed(left.resultdef) then
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case left.resultdef.size of
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8:
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emit_none(A_CQO,S_NO);
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4:
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emit_none(A_CDQ,S_NO);
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else
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internalerror(2013102701);
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end
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else
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emit_reg_reg(A_XOR,opsize,regd,regd);
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{Division depends on the right type.}
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if is_signed(right.resultdef) then
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op:=A_IDIV
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else
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op:=A_DIV;
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,opsize,right.location.reference)
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else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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emit_reg(op,opsize,right.location.register)
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else
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
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emit_reg(op,opsize,hreg1);
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end;
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{ Copy the result into a new register. Release R/EAX & R/EDX.}
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cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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if nodetype=divn then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
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else
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
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end;
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end;
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{*****************************************************************************
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{*****************************************************************************
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TX8664SHLRSHRNODE
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TX8664SHLRSHRNODE
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@ -241,7 +121,7 @@ implementation
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begin
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begin
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cunaryminusnode:=tx8664unaryminusnode;
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cunaryminusnode:=tx8664unaryminusnode;
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cmoddivnode:=tx8664moddivnode;
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cmoddivnode:=tx86moddivnode;
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cshlshrnode:=tx8664shlshrnode;
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cshlshrnode:=tx8664shlshrnode;
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cnotnode:=tx8664notnode;
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cnotnode:=tx8664notnode;
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end.
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end.
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