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* implemented UseAVX512 properly

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+ make use of VREDUCE* for frac(...) if AVX512QD is a available

git-svn-id: trunk@47840 -
This commit is contained in:
florian 2020-12-23 17:25:09 +00:00
parent b28aa5c684
commit b713c7380b
3 changed files with 21 additions and 10 deletions
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3
compiler/x86/cpubase.pas
View File

@ -960,8 +960,7 @@ implementation
function UseAVX512: boolean;
begin
// Result:=(current_settings.fputype in fpu_avx_instructionsets) {$ifndef i8086}or (CPUX86_HAS_AVXUNIT in cpu_capabilities[current_settings.cputype]){$endif i8086};
Result:=false;
Result:={$ifdef i8086}false{$else i8086}UseAVX and (FPUX86_HAS_AVX512F in fpu_capabilities[current_settings.fputype]){$endif i8086};
end;

22
compiler/x86/nx86inl.pas
View File

@ -1315,15 +1315,25 @@ implementation
case tfloatdef(left.resultdef).floattype of
s32real:
begin
{ using left.location.register here as 3rd parameter is crucial to break dependency chains }
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VROUNDSS,S_NO,3,left.location.register,left.location.register,location.register));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSUBSS,S_NO,location.register,left.location.register,location.register));
if UseAVX512 and (FPUX86_HAS_AVX512DQ in fpu_capabilities[current_settings.fputype]) then
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VREDUCESS,S_NO,3,left.location.register,left.location.register,location.register))
else
begin
{ using left.location.register here as 3rd parameter is crucial to break dependency chains }
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VROUNDSS,S_NO,3,left.location.register,left.location.register,location.register));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSUBSS,S_NO,location.register,left.location.register,location.register));
end;
end;
s64real:
begin
{ using left.location.register here as 3rd parameter is crucial to break dependency chains }
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VROUNDSD,S_NO,3,left.location.register,left.location.register,location.register));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSUBSD,S_NO,location.register,left.location.register,location.register));
if UseAVX512 and (FPUX86_HAS_AVX512DQ in fpu_capabilities[current_settings.fputype]) then
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VREDUCESD,S_NO,3,left.location.register,left.location.register,location.register))
else
begin
{ using left.location.register here as 3rd parameter is crucial to break dependency chains }
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg_reg_reg(A_VROUNDSD,S_NO,3,left.location.register,left.location.register,location.register));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSUBSD,S_NO,location.register,left.location.register,location.register));
end;
end;
else
internalerror(2017052102);

6
compiler/x86_64/cpuinfo.pas
View File

@ -182,7 +182,9 @@ type
tfpuflags =
(FPUX86_HAS_AVXUNIT,
FPUX86_HAS_32MMREGS,
FPUX86_HAS_AVX512F
FPUX86_HAS_AVX512F,
FPUX86_HAS_AVX512VL,
FPUX86_HAS_AVX512DQ
);
const
@ -203,7 +205,7 @@ type
{ fpu_sse42 } [],
{ fpu_avx } [FPUX86_HAS_AVXUNIT],
{ fpu_avx2 } [FPUX86_HAS_AVXUNIT],
{ fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_32MMREGS,FPUX86_HAS_AVX512F]
{ fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_32MMREGS,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
);
Implementation