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+ llvm support for the register allocator. While llvm works with virtual
registers itself, it requires them to be in SSA form. Therefore we
spill all registers that are written more than once to memory.
+ support in the generic register allocator for generating code that is
SSA-safe
+ spilling helpers for llvm
git-svn-id: branches/hlcgllvm@26044 -
This commit is contained in:
Jonas Maebe
parent
5ef93e85b8
commit
b7803ab974
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -322,6 +322,7 @@ compiler/llvm/llvmdef.pas svneol=native#text/plain
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compiler/llvm/llvminfo.pas svneol=native#text/plain
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compiler/llvm/llvmpara.pas svneol=native#text/plain
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compiler/llvm/llvmsym.pas svneol=native#text/plain
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compiler/llvm/rgllvm.pas svneol=native#text/plain
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compiler/llvm/tgllvm.pas svneol=native#text/plain
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compiler/m68k/aasmcpu.pas svneol=native#text/plain
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compiler/m68k/ag68kgas.pas svneol=native#text/plain
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@ -100,6 +100,10 @@ interface
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{$endif cpuextended}
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procedure loadcond(opidx: longint; _cond: topcmp);
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procedure loadfpcond(opidx: longint; _fpcond: tllvmfpcmp);
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{ register spilling code }
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function spilling_get_operation_type(opnr: longint): topertype;override;
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function spilling_get_reg_type(opnr: longint): tdef;
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end;
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@ -252,6 +256,160 @@ uses
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end;
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function taillvm.spilling_get_operation_type(opnr: longint): topertype;
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begin
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case llvmopcode of
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la_ret, la_br, la_switch, la_indirectbr,
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la_invoke, la_resume,
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la_unreachable,
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la_store,
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la_fence,
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la_cmpxchg,
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la_atomicrmw:
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begin
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{ instructions that never have a result }
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result:=operand_read;
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end;
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la_alloca,
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la_trunc, la_zext, la_sext, la_fptrunc, la_fpext,
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la_fptoui, la_fptosi, la_uitofp, la_sitofp,
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la_ptrtoint, la_inttoptr,
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la_bitcast,
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la_add, la_fadd, la_sub, la_fsub, la_mul, la_fmul,
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la_udiv,la_sdiv, la_fdiv, la_urem, la_srem, la_frem,
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la_shl, la_lshr, la_ashr, la_and, la_or, la_xor,
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la_extractelement, la_insertelement, la_shufflevector,
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la_extractvalue, la_insertvalue,
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la_getelementptr,
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la_load,
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la_icmp, la_fcmp,
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la_phi, la_select, la_call,
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la_va_arg, la_landingpad:
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begin
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if opnr=0 then
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result:=operand_write
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else
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result:=operand_read;
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end;
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else
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internalerror(2013103101)
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end;
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end;
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function taillvm.spilling_get_reg_type(opnr: longint): tdef;
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begin
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case llvmopcode of
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la_trunc, la_zext, la_sext, la_fptrunc, la_fpext,
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la_fptoui, la_fptosi, la_uitofp, la_sitofp,
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la_ptrtoint, la_inttoptr,
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la_bitcast:
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begin
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{ toreg = bitcast fromsize fromreg to tosize }
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case opnr of
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0: result:=oper[3]^.def;
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2: result:=oper[1]^.def
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else
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internalerror(2013103102);
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end;
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end;
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la_ret, la_switch, la_indirectbr,
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la_resume:
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begin
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{ ret size reg }
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if opnr=1 then
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result:=oper[0]^.def
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else
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internalerror(2013110101);
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end;
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la_invoke, la_call:
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begin
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internalerror(2013110102);
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end;
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la_br,
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la_unreachable:
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internalerror(2013110103);
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la_store:
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begin
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case opnr of
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1: result:=oper[0]^.def;
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{ type of the register in the reference }
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3: result:=oper[2]^.def;
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else
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internalerror(2013110104);
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end;
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end;
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la_load,
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la_getelementptr:
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begin
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{ dst = load ptrdef srcref }
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case opnr of
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0: result:=tpointerdef(oper[1]^.def).pointeddef;
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2: result:=oper[1]^.def;
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else
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internalerror(2013110105);
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end;
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end;
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la_fence,
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la_cmpxchg,
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la_atomicrmw:
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begin
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internalerror(2013110610);
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end;
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la_add, la_fadd, la_sub, la_fsub, la_mul, la_fmul,
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la_udiv,la_sdiv, la_fdiv, la_urem, la_srem, la_frem,
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la_shl, la_lshr, la_ashr, la_and, la_or, la_xor:
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begin
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case opnr of
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0,2,3:
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result:=oper[1]^.def;
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else
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internalerror(2013110106);
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end;
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end;
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la_extractelement, la_insertelement, la_shufflevector,
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la_extractvalue:
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begin
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{ todo }
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internalerror(2013110107);
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end;
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la_insertvalue:
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begin
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case opnr of
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0,2: result:=oper[1]^.def;
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else
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internalerror(2013110108);
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end;
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end;
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la_icmp, la_fcmp:
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begin
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case opnr of
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0: result:=pasbool8type;
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3,4: result:=oper[2]^.def;
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else
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internalerror(2013110801);
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end
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end;
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la_alloca:
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begin
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{ shouldn't be spilled, the result of alloca should be read-only }
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internalerror(2013110109);
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end;
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la_select:
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begin
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case opnr of
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0,4,6: result:=oper[3]^.def;
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2: result:=oper[1]^.def;
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else
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internalerror(2013110110);
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end;
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end;
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else
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internalerror(2013103101)
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end;
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end;
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constructor taillvm.op_size(op : tllvmop; size: tdef);
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begin
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create_llvm(op);
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189
compiler/llvm/rgllvm.pas
Normal file
189
compiler/llvm/rgllvm.pas
Normal file
@ -0,0 +1,189 @@
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{
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Copyright (c) 2013 by Jonas Maebe, member of the Free Pascal development
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team
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This unit implements the LLVM-specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************}
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unit rgllvm;
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{$i fpcdefs.inc}
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interface
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uses
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aasmcpu,aasmtai,aasmdata,
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symtype,
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cgbase,cgutils,
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cpubase,llvmbase,
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rgobj;
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type
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{ trgllvm }
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trgllvm=class(trgobj)
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constructor create(Aregtype: Tregistertype; Adefaultsub: Tsubregister; const Ausable: array of tsuperregister; Afirst_imaginary: Tsuperregister; Apreserved_by_proc: Tcpuregisterset); reintroduce;
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procedure do_register_allocation(list: TAsmList; headertai: tai); override;
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procedure do_spill_read(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
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procedure do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
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protected
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procedure determine_spill_registers(list: TasmList; headertai: tai); override;
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procedure get_spill_temp(list:TAsmlist;spill_temps: Pspill_temp_list; supreg: tsuperregister);override;
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strict protected
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type
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tregwrites = (rw_none, rw_one, rw_multiple);
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pwrittenregs = ^twrittenregs;
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twrittenregs = bitpacked array[tsuperregister] of tregwrites;
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var
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spillcounter: longint;
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writtenregs: pwrittenregs;
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end;
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implementation
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uses
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verbose,cutils,
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globtype,globals,
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symdef,
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aasmllvm,
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tgobj;
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{ trgllvm }
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constructor trgllvm.create(Aregtype: Tregistertype; Adefaultsub: Tsubregister; const Ausable: array of tsuperregister; Afirst_imaginary: Tsuperregister; Apreserved_by_proc: Tcpuregisterset);
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begin
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inherited;
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{ tell the generic register allocator to generate SSA spilling code }
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ssa_safe:=true;
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end;
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procedure trgllvm.do_register_allocation(list: TAsmList; headertai: tai);
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begin
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{ these are SSA by design, they're only assigned by alloca
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instructions }
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if regtype=R_TEMPREGISTER then
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exit;
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inherited;
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end;
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procedure trgllvm.do_spill_read(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister);
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var
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ins: taillvm;
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def: tdef;
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begin
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def:=tdef(reginfo[orgsupreg].def);
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if not assigned(def) then
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internalerror(2013110803);
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ins:=taillvm.op_reg_size_ref(la_load,tempreg,getpointerdef(def),spilltemp);
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list.insertafter(ins,pos);
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{$ifdef DEBUG_SPILLING}
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list.Insertbefore(tai_comment.Create(strpnew('Spilling: Spill Read')),ins);
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{$endif}
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end;
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procedure trgllvm.do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister);
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var
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ins: taillvm;
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def: tdef;
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begin
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def:=tdef(reginfo[orgsupreg].def);
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if not assigned(def) then
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internalerror(2013110802);
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ins:=taillvm.op_size_reg_size_ref(la_store,def,tempreg,getpointerdef(def),spilltemp);
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list.insertafter(ins,pos);
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{$ifdef DEBUG_SPILLING}
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list.Insertbefore(tai_comment.Create(strpnew('Spilling: Spill Write')),ins);
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{$endif}
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end;
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procedure trgllvm.determine_spill_registers(list: TasmList; headertai: tai);
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var
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hp: tai;
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reg: tregister;
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sr: tsuperregister;
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i: longint;
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begin
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spillednodes.clear;
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{ there should be only one round of spilling per register type, we
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shouldn't generate multiple writes so a single register here }
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if spillcounter<>0 then
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exit;
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{ registers must be in SSA form -> determine all registers that are
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written to more than once }
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hp:=headertai;
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{ 2 bits per superregister, rounded up to a byte }
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writtenregs:=allocmem((maxreg*2+7) shr 3);
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while assigned(hp) do
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begin
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case hp.typ of
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ait_llvmins:
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begin
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for i:=0 to taillvm(hp).ops-1 do
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if (taillvm(hp).oper[i]^.typ=top_reg) and
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(getregtype(taillvm(hp).oper[i]^.reg)=regtype) and
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(taillvm(hp).spilling_get_operation_type(i)=operand_write) then
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begin
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reg:=taillvm(hp).oper[i]^.reg;
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sr:=getsupreg(reg);
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if writtenregs^[sr]<rw_multiple then
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writtenregs^[sr]:=succ(writtenregs^[sr]);
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end;
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end;
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end;
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hp:=tai(hp.next);
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end;
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{ add all registers with multiple writes to the spilled nodes }
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for sr:=0 to maxreg-1 do
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if writtenregs^[sr]=rw_multiple then
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spillednodes.add(sr);
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freemem(writtenregs);
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end;
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procedure trgllvm.get_spill_temp(list: TAsmlist; spill_temps: Pspill_temp_list; supreg: tsuperregister);
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var
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supstart: tai;
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i: longint;
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def: tdef;
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begin
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supstart:=live_start[supreg];
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if supstart.typ<>ait_llvmins then
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internalerror(2013110701);
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{ determine type of register so we can allocate a temp of the right
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type }
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def:=nil;
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for i:=0 to taillvm(supstart).ops-1 do
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begin
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if (taillvm(supstart).oper[i]^.typ=top_reg) and
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(getsupreg(taillvm(supstart).oper[i]^.reg)=supreg) then
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begin
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def:=taillvm(supstart).spilling_get_reg_type(i);
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break
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end;
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end;
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if not assigned(def) then
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internalerror(2013110702);
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tg.gethltemp(list,def,def.size,tt_noreuse,spill_temps^[supreg]);
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{ record for use in spill instructions }
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reginfo[supreg].def:=def;
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end;
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end.
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@ -101,6 +101,9 @@ unit rgobj;
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degree : TSuperregister;
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flags : Treginfoflagset;
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weight : longint;
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{$ifdef llvm}
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def : pointer;
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{$endif llvm}
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end;
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Preginfo=^TReginfo;
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@ -111,10 +114,14 @@ unit rgobj;
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register that will have to replace it }
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spillregconstraints : set of TSubRegister;
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orgreg : tsuperregister;
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tempreg : tregister;
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regread,regwritten, mustbespilled: boolean;
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loadreg,
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storereg: tregister;
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regread, regwritten, mustbespilled: boolean;
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end;
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tspillregsinfo = record
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reginfocount: longint;
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reginfo: array[0..3] of tspillreginfo;
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end;
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tspillregsinfo = array[0..3] of tspillreginfo;
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Pspill_temp_list=^Tspill_temp_list;
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Tspill_temp_list=array[tsuperregister] of Treference;
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@ -132,6 +139,8 @@ unit rgobj;
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trgobj=class
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preserved_by_proc : tcpuregisterset;
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used_in_proc : tcpuregisterset;
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{ generate SSA code? }
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ssa_safe: boolean;
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constructor create(Aregtype:Tregistertype;
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Adefaultsub:Tsubregister;
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@ -397,8 +406,9 @@ unit rgobj;
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regtype:=Aregtype;
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defaultsub:=Adefaultsub;
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preserved_by_proc:=Apreserved_by_proc;
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// default value set by newinstance
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// default values set by newinstance
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// used_in_proc:=[];
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// ssa_safe:=false;
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live_registers.init;
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{ Get reginfo for CPU registers }
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maxreginfo:=first_imaginary;
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@ -1975,6 +1985,9 @@ unit rgobj;
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end;
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end;
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end;
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{$ifdef llvm}
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ait_llvmins,
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{$endif llvm}
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ait_instruction:
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with tai_cpu_abstract_sym(p) do
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begin
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@ -2038,61 +2051,64 @@ unit rgobj;
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const r:Tsuperregisterset;
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const spilltemplist:Tspill_temp_list): boolean;
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var
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counter, regindex: longint;
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counter: longint;
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regs: tspillregsinfo;
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spilled: boolean;
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procedure addreginfo(reg: tregister; operation: topertype);
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var
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i, tmpindex: longint;
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supreg : tsuperregister;
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supreg: tsuperregister;
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begin
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tmpindex := regindex;
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supreg:=get_alias(getsupreg(reg));
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tmpindex := regs.reginfocount;
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supreg := get_alias(getsupreg(reg));
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{ did we already encounter this register? }
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for i := 0 to pred(regindex) do
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if (regs[i].orgreg = supreg) then
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for i := 0 to pred(regs.reginfocount) do
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if (regs.reginfo[i].orgreg = supreg) then
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begin
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tmpindex := i;
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break;
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end;
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if tmpindex > high(regs) then
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if tmpindex > high(regs.reginfo) then
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internalerror(2003120301);
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regs[tmpindex].orgreg := supreg;
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include(regs[tmpindex].spillregconstraints,get_spill_subreg(reg));
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regs.reginfo[tmpindex].orgreg := supreg;
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include(regs.reginfo[tmpindex].spillregconstraints,get_spill_subreg(reg));
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if supregset_in(r,supreg) then
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begin
|
||||
{ add/update info on this register }
|
||||
regs[tmpindex].mustbespilled := true;
|
||||
regs.reginfo[tmpindex].mustbespilled := true;
|
||||
case operation of
|
||||
operand_read:
|
||||
regs[tmpindex].regread := true;
|
||||
regs.reginfo[tmpindex].regread := true;
|
||||
operand_write:
|
||||
regs[tmpindex].regwritten := true;
|
||||
regs.reginfo[tmpindex].regwritten := true;
|
||||
operand_readwrite:
|
||||
begin
|
||||
regs[tmpindex].regread := true;
|
||||
regs[tmpindex].regwritten := true;
|
||||
regs.reginfo[tmpindex].regread := true;
|
||||
regs.reginfo[tmpindex].regwritten := true;
|
||||
end;
|
||||
end;
|
||||
spilled := true;
|
||||
end;
|
||||
inc(regindex,ord(regindex=tmpindex));
|
||||
inc(regs.reginfocount,ord(regs.reginfocount=tmpindex));
|
||||
end;
|
||||
|
||||
|
||||
procedure tryreplacereg(var reg: tregister);
|
||||
procedure tryreplacereg(var reg: tregister; useloadreg: boolean);
|
||||
var
|
||||
i: longint;
|
||||
supreg: tsuperregister;
|
||||
begin
|
||||
supreg:=get_alias(getsupreg(reg));
|
||||
for i:=0 to pred(regindex) do
|
||||
if (regs[i].mustbespilled) and
|
||||
(regs[i].orgreg=supreg) then
|
||||
for i:=0 to pred(regs.reginfocount) do
|
||||
if (regs.reginfo[i].mustbespilled) and
|
||||
(regs.reginfo[i].orgreg=supreg) then
|
||||
begin
|
||||
{ Only replace supreg }
|
||||
setsupreg(reg,getsupreg(regs[i].tempreg));
|
||||
if useloadreg then
|
||||
setsupreg(reg,getsupreg(regs.reginfo[i].loadreg))
|
||||
else
|
||||
setsupreg(reg,getsupreg(regs.reginfo[i].storereg));
|
||||
break;
|
||||
end;
|
||||
end;
|
||||
@ -2105,10 +2121,13 @@ unit rgobj;
|
||||
begin
|
||||
result := false;
|
||||
fillchar(regs,sizeof(regs),0);
|
||||
for counter := low(regs) to high(regs) do
|
||||
regs[counter].orgreg := RS_INVALID;
|
||||
for counter := low(regs.reginfo) to high(regs.reginfo) do
|
||||
begin
|
||||
regs.reginfo[counter].orgreg := RS_INVALID;
|
||||
regs.reginfo[counter].loadreg := NR_INVALID;
|
||||
regs.reginfo[counter].storereg := NR_INVALID;
|
||||
end;
|
||||
spilled := false;
|
||||
regindex := 0;
|
||||
|
||||
{ check whether and if so which and how (read/written) this instructions contains
|
||||
registers that must be spilled }
|
||||
@ -2160,8 +2179,8 @@ unit rgobj;
|
||||
|
||||
For non-x86 it is nevertheless possible to replace moves to/from the register
|
||||
with loads/stores to spilltemp (Sergei) }
|
||||
for counter := 0 to pred(regindex) do
|
||||
with regs[counter] do
|
||||
for counter := 0 to pred(regs.reginfocount) do
|
||||
with regs.reginfo[counter] do
|
||||
begin
|
||||
if mustbespilled then
|
||||
begin
|
||||
@ -2229,54 +2248,66 @@ unit rgobj;
|
||||
loadpos:=tai(loadpos.next);
|
||||
|
||||
{ Load the spilled registers }
|
||||
for counter := 0 to pred(regindex) do
|
||||
with regs[counter] do
|
||||
for counter := 0 to pred(regs.reginfocount) do
|
||||
with regs.reginfo[counter] do
|
||||
begin
|
||||
if mustbespilled and regread then
|
||||
begin
|
||||
tempreg:=getregisterinline(list,regs[counter].spillregconstraints);
|
||||
do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],tempreg,orgreg);
|
||||
loadreg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints);
|
||||
do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],loadreg,orgreg);
|
||||
end;
|
||||
end;
|
||||
|
||||
{ Release temp registers of read-only registers, and add reference of the instruction
|
||||
to the reginfo }
|
||||
for counter := 0 to pred(regindex) do
|
||||
with regs[counter] do
|
||||
for counter := 0 to pred(regs.reginfocount) do
|
||||
with regs.reginfo[counter] do
|
||||
begin
|
||||
if mustbespilled and regread and (not regwritten) then
|
||||
if mustbespilled and regread and
|
||||
(ssa_safe or
|
||||
not regwritten) then
|
||||
begin
|
||||
{ The original instruction will be the next that uses this register }
|
||||
add_reg_instruction(instr,tempreg,1);
|
||||
ungetregisterinline(list,tempreg);
|
||||
add_reg_instruction(instr,loadreg,1);
|
||||
ungetregisterinline(list,loadreg);
|
||||
end;
|
||||
end;
|
||||
|
||||
{ Allocate temp registers of write-only registers, and add reference of the instruction
|
||||
to the reginfo }
|
||||
for counter := 0 to pred(regindex) do
|
||||
with regs[counter] do
|
||||
for counter := 0 to pred(regs.reginfocount) do
|
||||
with regs.reginfo[counter] do
|
||||
begin
|
||||
if mustbespilled and regwritten then
|
||||
begin
|
||||
{ When the register is also loaded there is already a register assigned }
|
||||
if (not regread) then
|
||||
tempreg:=getregisterinline(list,regs[counter].spillregconstraints);
|
||||
if (not regread) or
|
||||
ssa_safe then
|
||||
begin
|
||||
storereg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints);
|
||||
{ we also use loadreg for store replacements in case we
|
||||
don't have ensure ssa -> initialise loadreg even if
|
||||
there are no reads }
|
||||
if not regread then
|
||||
loadreg:=storereg;
|
||||
end
|
||||
else
|
||||
storereg:=loadreg;
|
||||
{ The original instruction will be the next that uses this register, this
|
||||
also needs to be done for read-write registers }
|
||||
add_reg_instruction(instr,tempreg,1);
|
||||
add_reg_instruction(instr,storereg,1);
|
||||
end;
|
||||
end;
|
||||
|
||||
{ store the spilled registers }
|
||||
storepos:=tai(instr.next);
|
||||
for counter := 0 to pred(regindex) do
|
||||
with regs[counter] do
|
||||
for counter := 0 to pred(regs.reginfocount) do
|
||||
with regs.reginfo[counter] do
|
||||
begin
|
||||
if mustbespilled and regwritten then
|
||||
begin
|
||||
do_spill_written(list,tai(storepos.previous),spilltemplist[orgreg],tempreg,orgreg);
|
||||
ungetregisterinline(list,tempreg);
|
||||
do_spill_written(list,tai(storepos.previous),spilltemplist[orgreg],storereg,orgreg);
|
||||
ungetregisterinline(list,storereg);
|
||||
end;
|
||||
end;
|
||||
|
||||
@ -2293,7 +2324,8 @@ unit rgobj;
|
||||
top_reg:
|
||||
begin
|
||||
if (getregtype(reg) = regtype) then
|
||||
tryreplacereg(reg);
|
||||
tryreplacereg(reg,not ssa_safe or
|
||||
(instr.spilling_get_operation_type(counter)=operand_read));
|
||||
end;
|
||||
top_ref:
|
||||
begin
|
||||
@ -2301,14 +2333,16 @@ unit rgobj;
|
||||
begin
|
||||
if (ref^.base <> NR_NO) and
|
||||
(getregtype(ref^.base)=regtype) then
|
||||
tryreplacereg(ref^.base);
|
||||
tryreplacereg(ref^.base,
|
||||
not ssa_safe or (instr.spilling_get_operation_type_ref(counter,ref^.base)=operand_read));
|
||||
if (ref^.index <> NR_NO) and
|
||||
(getregtype(ref^.index)=regtype) then
|
||||
tryreplacereg(ref^.index);
|
||||
tryreplacereg(ref^.index,
|
||||
not ssa_safe or (instr.spilling_get_operation_type_ref(counter,ref^.index)=operand_read));
|
||||
{$if defined(x86) or defined(m68k)}
|
||||
if (ref^.segment <> NR_NO) and
|
||||
(getregtype(ref^.segment)=regtype) then
|
||||
tryreplacereg(ref^.segment);
|
||||
tryreplacereg(ref^.segment,true { always read-only });
|
||||
{$endif defined(x86) or defined(m68k)}
|
||||
end;
|
||||
end;
|
||||
@ -2316,7 +2350,7 @@ unit rgobj;
|
||||
top_shifterop:
|
||||
begin
|
||||
if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then
|
||||
tryreplacereg(shifterop^.rs);
|
||||
tryreplacereg(shifterop^.rs,true { always read-only });
|
||||
end;
|
||||
{$endif ARM}
|
||||
end;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user