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+ added WebAssembly intrinsics for reading __tls_size, __tls_align and __tls_base

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Nikolay Nikolov 2022-07-14 04:15:47 +03:00
parent 7475d22154
commit b900be6142
4 changed files with 46 additions and 2 deletions
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6
compiler/wasm32/ccpuinnr.inc
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@ -93,5 +93,9 @@
in_i64_atomic_store8 = in_cpu_first+69,
in_i64_atomic_store16 = in_cpu_first+70,
in_i64_atomic_store32 = in_cpu_first+71,
in_i64_atomic_store = in_cpu_first+72
in_i64_atomic_store = in_cpu_first+72,
in_wasm32_tls_size = in_cpu_first+73,
in_wasm32_tls_align = in_cpu_first+74,
in_wasm32_tls_base = in_cpu_first+75

34
compiler/wasm32/nwasminl.pas
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@ -58,6 +58,7 @@ interface
procedure second_atomic_store(op: TAsmOp);
procedure second_atomic_rmw_x_y(op: TAsmOp);
procedure second_atomic_rmw_x_y_z(op: TAsmOp);
procedure second_tls_get(const SymStr: string);
protected
function first_sqr_real: tnode; override;
public
@ -541,6 +542,17 @@ implementation
end;
procedure twasminlinenode.second_tls_get(const SymStr: string);
begin
current_asmdata.CurrAsmList.Concat(taicpu.op_sym(a_global_get,current_asmdata.RefAsmSymbol(SymStr,AT_WASM_GLOBAL)));
thlcgwasm(hlcg).incstack(current_asmdata.CurrAsmList,1);
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
thlcgwasm(hlcg).a_load_stack_loc(current_asmdata.CurrAsmList,resultdef,location);
end;
function twasminlinenode.first_sqr_real: tnode;
begin
expectloc:=LOC_FPUREGISTER;
@ -690,6 +702,17 @@ implementation
CheckParameters(2);
resultdef:=voidtype;
end;
in_wasm32_tls_size,
in_wasm32_tls_align:
begin
CheckParameters(0);
resultdef:=u32inttype;
end;
in_wasm32_tls_base:
begin
CheckParameters(0);
resultdef:=voidpointertype;
end;
else
Result:=inherited pass_typecheck_cpu;
end;
@ -774,7 +797,10 @@ implementation
in_i64_atomic_load8_u,
in_i64_atomic_load16_u,
in_i64_atomic_load32_u,
in_i64_atomic_load:
in_i64_atomic_load,
in_wasm32_tls_size,
in_wasm32_tls_align,
in_wasm32_tls_base:
expectloc:=LOC_REGISTER;
else
Result:=inherited first_cpu;
@ -931,6 +957,12 @@ implementation
second_atomic_store(a_i64_atomic_store32);
in_i64_atomic_store:
second_atomic_store(a_i64_atomic_store);
in_wasm32_tls_size:
second_tls_get(TLS_SIZE_SYM);
in_wasm32_tls_align:
second_tls_get(TLS_ALIGN_SYM);
in_wasm32_tls_base:
second_tls_get(TLS_BASE_SYM);
else
inherited pass_generate_code_cpu;
end;

4
rtl/wasm32/cpuh.inc
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@ -101,3 +101,7 @@ procedure fpc_wasm32_i64_atomic_store16(Dest: PWord; x: QWord);[internproc:fpc_i
procedure fpc_wasm32_i64_atomic_store32(Dest: PLongWord; x: QWord);[internproc:fpc_in_i64_atomic_store32];
procedure fpc_wasm32_i64_atomic_store(Dest: PQWord; x: QWord);[internproc:fpc_in_i64_atomic_store];
function fpc_wasm32_tls_size: SizeUInt;[internproc:fpc_in_wasm32_tls_size];
function fpc_wasm32_tls_align: SizeUInt;[internproc:fpc_in_wasm32_tls_align];
function fpc_wasm32_tls_base: Pointer;[internproc:fpc_in_wasm32_tls_base];

4
rtl/wasm32/cpuinnr.inc
View File

@ -95,3 +95,7 @@
fpc_in_i64_atomic_store32 = fpc_in_cpu_first+71;
fpc_in_i64_atomic_store = fpc_in_cpu_first+72;
fpc_in_wasm32_tls_size = fpc_in_cpu_first+73;
fpc_in_wasm32_tls_align = fpc_in_cpu_first+74;
fpc_in_wasm32_tls_base = fpc_in_cpu_first+75;