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* m68k: initial support for ROL/ROR operations, defining 'cpurox' for CPU target can actually enable them. However it cannot be done outright because these instructions do not exits on Coldfire, and internal processing of RoX,Sar,BsX, etc. can not yet be switched depending on CPU subtype.

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git-svn-id: trunk@28101 -
This commit is contained in:
sergei 2014-06-29 17:49:30 +00:00
parent 15e374f3c6
commit b91d965096
2 changed files with 5 additions and 2 deletions
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1
compiler/m68k/aasmcpu.pas
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@ -469,6 +469,7 @@ type
result:=operand_write;
A_ADD, A_ADDQ, A_ADDX, A_SUB, A_SUBQ, A_SUBX,
A_AND, A_LSR, A_LSL, A_ASR, A_ASL, A_EOR, A_EORI, A_OR,
A_ROL, A_ROR, A_ROXL, A_ROXR,
A_MULS, A_MULU, A_DIVS, A_DIVU, A_DIVSL, A_DIVUL:
if opnr=1 then
result:=operand_readwrite;

6
compiler/m68k/cgcpu.pas
View File

@ -152,8 +152,8 @@ unit cgcpu;
A_LSR,
A_SUB,
A_EOR,
A_NONE,
A_NONE
A_ROL,
A_ROR
);
{ opcode with extend bits table lookup, used by 64bit cg }
@ -1092,6 +1092,8 @@ unit cgcpu;
call_rtl_mul_const_reg(list, size, a, reg,'fpc_mul_longint');
end;
end;
OP_ROL,
OP_ROR,
OP_SAR,
OP_SHL,
OP_SHR :