From b9431c876e7fb1483c01db5ecc39be8b4d0754fd Mon Sep 17 00:00:00 2001
From: yury <jura@cp-lab.com>
Date: Wed, 23 Apr 2008 08:22:27 +0000
Subject: [PATCH] * More complete fix for bug #10515. Thanks to Jonas for
 suggestion. * Fixed warnings in tcnvint6.pp

git-svn-id: trunk@10765 -
---
 compiler/arm/cgcpu.pas    | 17 +++++++++++++++++
 compiler/arm/narminl.pas  | 10 ----------
 tests/test/cg/tcnvint6.pp |  6 +++---
 3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas
index 86245fdb50..b8fca41bee 100644
--- a/compiler/arm/cgcpu.pas
+++ b/compiler/arm/cgcpu.pas
@@ -106,6 +106,11 @@ unit cgcpu;
         function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
 
         procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
+
+      private
+        { clear out potential overflow bits from 8 or 16 bit operations  }
+        { the upper 24/16 bits of a register after an operation          }
+        procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
       end;
 
       tcg64farm = class(tcg64f32)
@@ -476,6 +481,7 @@ unit cgcpu;
                 a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
               end;
           end;
+        maybeadjustresult(list,op,size,dst);
       end;
 
 
@@ -571,6 +577,7 @@ unit cgcpu;
                 taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
               ));
         end;
+        maybeadjustresult(list,op,size,dst);
       end;
 
 
@@ -1964,6 +1971,16 @@ unit cgcpu;
       end;
 
 
+    procedure tcgarm.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
+      const
+        overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NOT,OP_NEG];
+      begin
+        if (op in overflowops) and
+           (size in [OS_8,OS_S8,OS_16,OS_S16]) then
+          a_load_reg_reg(list,OS_32,size,dst,dst);
+      end;
+
+
     procedure tcg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
       begin
         case op of
diff --git a/compiler/arm/narminl.pas b/compiler/arm/narminl.pas
index c9abdc4293..7ba59454cb 100644
--- a/compiler/arm/narminl.pas
+++ b/compiler/arm/narminl.pas
@@ -49,7 +49,6 @@ interface
         procedure second_sin_real; override;
         }
         procedure second_prefetch; override;
-        procedure second_incdec; override;
       private
         procedure load_fpu_location;
       end;
@@ -225,15 +224,6 @@ implementation
       end;
 
 
-    procedure tarminlinenode.second_incdec;
-      begin
-        inherited second_incdec;
-        { Strip result if inc/dec is performed in register on value less than 32-bit }
-        with tcallparanode(left).left.location do
-          if (loc in [LOC_REGISTER,LOC_CREGISTER]) and (tcgsize2size[size]<sizeof(aint)) then
-            cg.a_load_reg_reg(current_asmdata.CurrAsmList, size, OS_32, register, register)
-      end;
-
 begin
   cinlinenode:=tarminlinenode;
 end.
diff --git a/tests/test/cg/tcnvint6.pp b/tests/test/cg/tcnvint6.pp
index 6e312a586a..328ed538a3 100644
--- a/tests/test/cg/tcnvint6.pp
+++ b/tests/test/cg/tcnvint6.pp
@@ -11,7 +11,7 @@ var
   c,c2: cardinal;
   shi,shi2: shortint;
   si,si2: smallint;
-  i64,i642: int64;
+  i64: int64;
 begin
   b:=$ff;
   Inc(b,$ff);
@@ -83,7 +83,7 @@ begin
   if i64<>$fffffffe then
     error(33);
 {$ifdef FPC}
-  if qword(shi)<>$fffffffffffffffe then
+  if qword(shi)<>qword($fffffffffffffffe) then
     error(34);
 {$endif FPC}
   shi2:=-2;
@@ -100,7 +100,7 @@ begin
   if i64<>$fffffffe then
     halt(43);
 {$ifdef FPC}
-  if qword(si)<>$fffffffffffffffe then
+  if qword(si)<>qword($fffffffffffffffe) then
     error(44);
 {$endif FPC}
   si2:=-2;