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* fixed stm and ldm to be usable with preindex operand
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@ -51,7 +51,8 @@ uses
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constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
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constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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constructor op_reg_const(op:tasmop; _op1: tregister; _op2: longint);
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constructor op_reg_regset(op:tasmop; _op1: tregister; _op2: tsuperregisterset);
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constructor op_ref_regset(op:tasmop; _op1: treference; _op2: tsuperregisterset);
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constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
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constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: Longint);
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@ -170,11 +171,11 @@ implementation
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end;
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constructor taicpu.op_reg_regset(op:tasmop; _op1: tregister; _op2: tsuperregisterset);
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constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; _op2: tsuperregisterset);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadref(0,_op1);
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loadregset(1,_op2);
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end;
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@ -365,7 +366,10 @@ implementation
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end.
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{
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$Log$
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Revision 1.10 2003-09-04 21:07:03 florian
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Revision 1.11 2003-09-06 11:21:49 florian
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* fixed stm and ldm to be usable with preindex operand
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Revision 1.10 2003/09/04 21:07:03 florian
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* ARM compiler compiles again
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Revision 1.9 2003/09/04 00:15:29 florian
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@ -203,7 +203,17 @@ unit agarmgas;
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// debug code
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// writeln(s);
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// writeln(taicpu(hp).fileinfo.line);
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s:=s+sep+getopstr(taicpu(hp).oper[i]);
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{ LDM and STM use references as first operand but they are written like a register }
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if (i=0) and (op in [A_LDM,A_STM]) then
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begin
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s:=s+sep+gas_regname(taicpu(hp).oper[0].ref^.index);
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if taicpu(hp).oper[0].ref^.addressmode=AM_PREINDEXED then
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s:=s+'!';
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end
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else
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s:=s+sep+getopstr(taicpu(hp).oper[i]);
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sep:=',';
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end;
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end;
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@ -216,7 +226,10 @@ begin
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end.
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{
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$Log$
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Revision 1.10 2003-09-05 23:57:01 florian
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Revision 1.11 2003-09-06 11:21:49 florian
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* fixed stm and ldm to be usable with preindex operand
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Revision 1.10 2003/09/05 23:57:01 florian
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* arm is working again as before the new register naming scheme was implemented
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Revision 1.9 2003/09/04 00:15:29 florian
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@ -694,6 +694,8 @@ unit cgcpu;
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procedure tcgarm.g_stackframe_entry(list : taasmoutput;localsize : longint);
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var
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ref : treference;
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begin
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LocalSize:=align(LocalSize,4);
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@ -702,8 +704,11 @@ unit cgcpu;
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a_reg_alloc(list,NR_R12);
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list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
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{ restore int registers and return }
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list.concat(setoppostfix(taicpu.op_reg_regset(A_STM,NR_STACK_POINTER_REG,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R12,RS_R15]),PF_FD));
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{ save int registers }
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reference_reset(ref);
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ref.index:=NR_STACK_POINTER_REG;
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ref.addressmode:=AM_PREINDEXED;
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list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R12,RS_R15]),PF_FD));
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list.concat(taicpu.op_reg_reg_const(A_SUB,NR_FRAME_POINTER_REG,NR_R12,4));
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a_reg_alloc(list,NR_R12);
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@ -714,12 +719,19 @@ unit cgcpu;
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procedure tcgarm.g_return_from_proc(list : taasmoutput;parasize : aword);
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var
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ref : treference;
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begin
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if (current_procinfo.framepointer=NR_STACK_POINTER_REG) then
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list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14))
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else
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{ restore int registers and return }
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list.concat(setoppostfix(taicpu.op_reg_regset(A_LDM,NR_R11,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
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begin
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{ restore int registers and return }
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reference_reset(ref);
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ref.index:=NR_FRAME_POINTER_REG;
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ref.addressmode:=AM_PREINDEXED;
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list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
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end;
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end;
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@ -1082,7 +1094,10 @@ begin
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end.
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{
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$Log$
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Revision 1.15 2003-09-05 23:57:01 florian
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Revision 1.16 2003-09-06 11:21:50 florian
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* fixed stm and ldm to be usable with preindex operand
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Revision 1.15 2003/09/05 23:57:01 florian
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* arm is working again as before the new register naming scheme was implemented
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Revision 1.14 2003/09/04 21:07:03 florian
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