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* SPARC: simplified and fixed a_load_const_reg method, was generating redundant instructions for constants with non-zero bits 10..12.

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git-svn-id: trunk@26318 -
This commit is contained in:
sergei 2013-12-30 09:59:41 +00:00
parent d2b8275b99
commit bf94257310
1 changed files with 2 additions and 4 deletions
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6
compiler/sparc/cgcpu.pas
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@ -415,15 +415,13 @@ implementation
instructions which would cause problems with the delay slot (FK) } instructions which would cause problems with the delay slot (FK) }
if (a=0) then if (a=0) then
list.concat(taicpu.op_reg(A_CLR,reg)) list.concat(taicpu.op_reg(A_CLR,reg))
{ sethi allows to set the upper 22 bit, so we'll take full advantage of it }
else if (aint(a) and aint($1fff))=0 then
list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg))
else if (a>=simm13lo) and (a<=simm13hi) then else if (a>=simm13lo) and (a<=simm13hi) then
list.concat(taicpu.op_const_reg(A_MOV,a,reg)) list.concat(taicpu.op_const_reg(A_MOV,a,reg))
else else
begin begin
list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg)); list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg));
list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg)); if (aint(a) and aint($3ff))<>0 then
list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
end; end;
end; end;