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* patch by J. Gareth Moreton: x86: RegLoadedWIthNewValue overhaul and bug fix, resolves #39187
git-svn-id: trunk@49588 -
This commit is contained in:
florian
parent
924f9466f0
commit
c185ce02cc
@ -1217,15 +1217,16 @@ unit aoptx86;
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function TX86AsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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p: taicpu absolute hp;
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i: Integer;
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begin
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Result := False;
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if not assigned(hp) or
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(hp.typ <> ait_instruction) then
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begin
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Result := false;
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exit;
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end;
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p := taicpu(hp);
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Exit;
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// p := taicpu(hp);
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Prefetch(insprop[p.opcode]);
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if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
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with insprop[p.opcode] do
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begin
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@ -1262,94 +1263,322 @@ unit aoptx86;
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end;
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exit;
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end;
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Result :=
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(((p.opcode = A_MOV) or
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(p.opcode = A_MOVZX) or
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(p.opcode = A_MOVSX) or
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(p.opcode = A_LEA) or
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(p.opcode = A_VMOVSS) or
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(p.opcode = A_VMOVSD) or
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(p.opcode = A_VMOVAPD) or
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(p.opcode = A_VMOVAPS) or
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(p.opcode = A_VMOVQ) or
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(p.opcode = A_MOVSS) or
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(p.opcode = A_MOVSD) or
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(p.opcode = A_MOVQ) or
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(p.opcode = A_MOVAPD) or
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(p.opcode = A_MOVAPS) or
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{$ifndef x86_64}
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(p.opcode = A_LDS) or
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(p.opcode = A_LES) or
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{$endif not x86_64}
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(p.opcode = A_LFS) or
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(p.opcode = A_LGS) or
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(p.opcode = A_LSS)) and
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(p.ops=2) and { A_MOVSD can have zero operands, so this check is needed }
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(p.oper[1]^.typ = top_reg) and
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(Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg)) and
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((p.oper[0]^.typ = top_const) or
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((p.oper[0]^.typ = top_reg) and
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not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
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((p.oper[0]^.typ = top_ref) and
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not RegInRef(reg,p.oper[0]^.ref^)))) or
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((p.opcode = A_POP) and
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(Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg))) or
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((p.opcode = A_IMUL) and
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(p.ops=3) and
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(Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg,reg)) and
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(((p.oper[1]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[1]^.reg,reg))) or
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((p.oper[1]^.typ=top_ref) and not(RegInRef(reg,p.oper[1]^.ref^))))) or
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((((p.opcode = A_IMUL) or
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(p.opcode = A_MUL)) and
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(p.ops=1)) and
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(((p.oper[0]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
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((p.oper[0]^.typ=top_ref) and not(RegInRef(reg,p.oper[0]^.ref^)))) and
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(((p.opsize=S_B) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
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((p.opsize=S_W) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
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((p.opsize=S_L) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg))
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{ Handle special cases first }
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case p.opcode of
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A_MOV, A_MOVZX, A_MOVSX, A_LEA, A_VMOVSS, A_VMOVSD, A_VMOVAPD,
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A_VMOVAPS, A_VMOVQ, A_MOVSS, A_MOVSD, A_MOVQ, A_MOVAPD, A_MOVAPS:
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begin
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Result :=
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(p.ops=2) and { A_MOVSD can have zero operands, so this check is needed }
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(p.oper[1]^.typ = top_reg) and
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(Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg)) and
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(
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(p.oper[0]^.typ = top_const) or
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(
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(p.oper[0]^.typ = top_reg) and
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not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))
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) or (
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(p.oper[0]^.typ = top_ref) and
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not RegInRef(reg,p.oper[0]^.ref^)
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)
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);
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end;
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A_MUL, A_IMUL:
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Result :=
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(
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(p.ops=3) and { IMUL only }
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(Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg,reg)) and
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(
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(
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(p.oper[1]^.typ=top_reg) and
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not Reg1ReadDependsOnReg2(p.oper[1]^.reg,reg)
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) or (
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(p.oper[1]^.typ=top_ref) and
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not RegInRef(reg,p.oper[1]^.ref^)
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)
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)
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) or (
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(
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(p.ops=1) and
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(
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(
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(
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(p.oper[0]^.typ=top_reg) and
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not Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg)
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)
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) or (
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(p.oper[0]^.typ=top_ref) and
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not RegInRef(reg,p.oper[0]^.ref^)
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)
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) and (
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(
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(p.opsize=S_B) and
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Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and
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not Reg1ReadDependsOnReg2(NR_AL,reg)
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) or (
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(p.opsize=S_W) and
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Reg1WriteOverwritesReg2Entirely(NR_DX,reg)
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) or (
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(p.opsize=S_L) and
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Reg1WriteOverwritesReg2Entirely(NR_EDX,reg)
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{$ifdef x86_64}
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or ((p.opsize=S_Q) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg))
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) or (
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(p.opsize=S_Q) and
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Reg1WriteOverwritesReg2Entirely(NR_RDX,reg)
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{$endif x86_64}
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)) or
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((p.opcode = A_CWD) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
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((p.opcode = A_CDQ) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg)) or
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{$ifdef x86_64}
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((p.opcode = A_CQO) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg)) or
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{$endif x86_64}
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((p.opcode = A_CBW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
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)
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)
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)
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);
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A_CBW:
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Result := Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg));
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{$ifndef x86_64}
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((p.opcode = A_LDS) and (reg=NR_DS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
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((p.opcode = A_LES) and (reg=NR_ES) and not(RegInRef(reg,p.oper[0]^.ref^))) or
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A_LDS:
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Result := (reg=NR_DS) and not(RegInRef(reg,p.oper[0]^.ref^));
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A_LES:
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Result := (reg=NR_ES) and not(RegInRef(reg,p.oper[0]^.ref^));
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{$endif not x86_64}
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((p.opcode = A_LFS) and (reg=NR_FS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
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((p.opcode = A_LGS) and (reg=NR_GS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
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((p.opcode = A_LSS) and (reg=NR_SS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
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{$ifndef x86_64}
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((p.opcode = A_AAM) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
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{$endif not x86_64}
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((p.opcode = A_LAHF) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
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((p.opcode = A_LODSB) and Reg1WriteOverwritesReg2Entirely(NR_AL,reg)) or
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((p.opcode = A_LODSW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg)) or
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((p.opcode = A_LODSD) and Reg1WriteOverwritesReg2Entirely(NR_EAX,reg)) or
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A_LFS:
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Result := (reg=NR_FS) and not(RegInRef(reg,p.oper[0]^.ref^));
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A_LGS:
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Result := (reg=NR_GS) and not(RegInRef(reg,p.oper[0]^.ref^));
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A_LSS:
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Result := (reg=NR_SS) and not(RegInRef(reg,p.oper[0]^.ref^));
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A_LAHF{$ifndef x86_64}, A_AAM{$endif not x86_64}:
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Result := Reg1WriteOverwritesReg2Entirely(NR_AH,reg);
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A_LODSB:
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Result := Reg1WriteOverwritesReg2Entirely(NR_AL,reg);
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A_LODSW:
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Result := Reg1WriteOverwritesReg2Entirely(NR_AX,reg);
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{$ifdef x86_64}
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((p.opcode = A_LODSQ) and Reg1WriteOverwritesReg2Entirely(NR_RAX,reg)) or
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A_LODSQ:
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Result := Reg1WriteOverwritesReg2Entirely(NR_RAX,reg);
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{$endif x86_64}
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((p.opcode = A_SETcc) and (p.oper[0]^.typ=top_reg) and Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
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(((p.opcode = A_FSTSW) or
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(p.opcode = A_FNSTSW)) and
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(p.oper[0]^.typ=top_reg) and
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Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
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(((p.opcode = A_SHRX) or (p.opcode = A_SHLX)) and
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(p.ops=3) and
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(Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg,reg)) and
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(((p.oper[1]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[1]^.reg,reg))) or
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((p.oper[1]^.typ=top_ref) and not(RegInRef(reg,p.oper[1]^.ref^)))) and
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(((p.oper[0]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
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((p.oper[0]^.typ=top_ref) and not(RegInRef(reg,p.oper[0]^.ref^))))) or
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(((p.opcode = A_XOR) or (p.opcode = A_SUB) or (p.opcode = A_SBB)) and
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(p.oper[0]^.typ=top_reg) and (p.oper[1]^.typ=top_reg) and
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(p.oper[0]^.reg=p.oper[1]^.reg) and
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Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg));
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A_LODSD:
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Result := Reg1WriteOverwritesReg2Entirely(NR_EAX,reg);
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A_FSTSW, A_FNSTSW:
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Result := (p.oper[0]^.typ=top_reg) and Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg);
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else
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begin
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with insprop[p.opcode] do
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begin
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if (
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{ xor %reg,%reg etc. is classed as a new value }
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(([Ch_NoReadIfEqualRegs]*Ch)<>[]) and
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MatchOpType(p, top_reg, top_reg) and
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(p.oper[0]^.reg = p.oper[1]^.reg) and
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Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg)
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) then
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begin
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Result := True;
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Exit;
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end;
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{ Make sure the entire register is overwritten }
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if (getregtype(reg) = R_INTREGISTER) then
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begin
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if (p.ops > 0) then
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begin
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if RegInOp(reg, p.oper[0]^) then
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begin
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if (p.oper[0]^.typ = top_ref) then
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begin
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if RegInRef(reg, p.oper[0]^.ref^) then
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begin
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Result := False;
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Exit;
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end;
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end
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else if (p.oper[0]^.typ = top_reg) then
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begin
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if ([Ch_ROp1, Ch_RWOp1, Ch_MOp1]*Ch<>[]) then
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begin
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Result := False;
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Exit;
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end
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else if ([Ch_WOp1]*Ch<>[]) then
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begin
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if Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg, reg) then
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Result := True
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else
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begin
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Result := False;
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Exit;
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end;
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end;
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end;
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end;
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if (p.ops > 1) then
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begin
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if RegInOp(reg, p.oper[1]^) then
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begin
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if (p.oper[1]^.typ = top_ref) then
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begin
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if RegInRef(reg, p.oper[1]^.ref^) then
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begin
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Result := False;
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Exit;
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end;
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end
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else if (p.oper[1]^.typ = top_reg) then
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begin
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if ([Ch_ROp2, Ch_RWOp2, Ch_MOp2]*Ch<>[]) then
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begin
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Result := False;
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Exit;
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end
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else if ([Ch_WOp2]*Ch<>[]) then
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begin
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if Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg, reg) then
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Result := True
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else
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begin
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Result := False;
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Exit;
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end;
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end;
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end;
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end;
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if (p.ops > 2) then
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begin
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if RegInOp(reg, p.oper[2]^) then
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begin
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if (p.oper[2]^.typ = top_ref) then
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begin
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if RegInRef(reg, p.oper[2]^.ref^) then
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begin
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Result := False;
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Exit;
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end;
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end
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else if (p.oper[2]^.typ = top_reg) then
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begin
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if ([Ch_ROp3, Ch_RWOp3, Ch_MOp3]*Ch<>[]) then
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begin
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Result := False;
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Exit;
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end
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else if ([Ch_WOp3]*Ch<>[]) then
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begin
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if Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg, reg) then
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Result := True
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else
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begin
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Result := False;
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Exit;
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end;
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end;
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end;
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end;
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if (p.ops > 3) and RegInOp(reg, p.oper[3]^) then
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begin
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if (p.oper[3]^.typ = top_ref) then
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begin
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if RegInRef(reg, p.oper[3]^.ref^) then
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begin
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Result := False;
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Exit;
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end;
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end
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else if (p.oper[3]^.typ = top_reg) then
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begin
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if ([Ch_ROp4, Ch_RWOp4, Ch_MOp4]*Ch<>[]) then
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begin
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Result := False;
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Exit;
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end
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else if ([Ch_WOp4]*Ch<>[]) then
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begin
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if Reg1WriteOverwritesReg2Entirely(p.oper[3]^.reg, reg) then
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Result := True
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else
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begin
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Result := False;
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Exit;
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end;
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end;
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end;
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end;
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end;
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end;
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end;
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{ Don't do these ones first in case an input operand is equal to an explicit output registers }
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case getsupreg(reg) of
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RS_EAX:
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if ([Ch_WEAX{$ifdef x86_64},Ch_WRAX{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EAX, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_ECX:
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if ([Ch_WECX{$ifdef x86_64},Ch_WRCX{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_ECX, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_EDX:
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if ([Ch_REDX{$ifdef x86_64},Ch_WRDX{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EDX, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_EBX:
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if ([Ch_WEBX{$ifdef x86_64},Ch_WRBX{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EBX, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_ESP:
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if ([Ch_WESP{$ifdef x86_64},Ch_WRSP{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_ESP, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_EBP:
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if ([Ch_WEBP{$ifdef x86_64},Ch_WRBP{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EBP, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_ESI:
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if ([Ch_WESI{$ifdef x86_64},Ch_WRSI{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_ESI, reg) then
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begin
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Result := True;
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Exit;
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end;
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RS_EDI:
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if ([Ch_WEDI{$ifdef x86_64},Ch_WRDI{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EDI, reg) then
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begin
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Result := True;
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Exit;
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end;
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||||
else
|
||||
;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -2191,7 +2420,7 @@ unit aoptx86;
|
||||
if (taicpu(hp1).opcode <> A_MOV) and (taicpu(hp1).opcode <> A_LEA) then
|
||||
{ Just to make a saving, since there are no more optimisations with MOVZX and MOVSX/D }
|
||||
Exit;
|
||||
end;
|
||||
end;
|
||||
end
|
||||
{ The RegInOp check makes sure that movl r/m,%reg1l; movzbl (%reg1l),%reg1l"
|
||||
and "movl r/m,%reg1; leal $1(%reg1,%reg2),%reg1" etc. are not incorrectly
|
||||
@ -2819,9 +3048,6 @@ unit aoptx86;
|
||||
if
|
||||
not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1) and
|
||||
not RegModifiedBetween(taicpu(p).oper[0]^.reg, hp1, hp2) and
|
||||
{ if we replace taicpu(p).oper[1]^.reg by taicpu(p).oper[0]^.reg,
|
||||
taicpu(p).oper[1]^.reg might not be modified in between }
|
||||
not RegModifiedBetween(CurrentReg, p, hp2) and
|
||||
DeepMovOpt(taicpu(p), taicpu(hp2)) then
|
||||
begin
|
||||
{ Just in case something didn't get modified (e.g. an
|
||||
@ -2835,7 +3061,11 @@ unit aoptx86;
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
|
||||
|
||||
if not RegUsedAfterInstruction(CurrentReg, hp2, TmpUsedRegs) then
|
||||
if
|
||||
{ Make sure the original register isn't still present
|
||||
and has been written to (e.g. with SHRX) }
|
||||
RegLoadedWithNewValue(CurrentReg, hp2) or
|
||||
not RegUsedAfterInstruction(CurrentReg, hp2, TmpUsedRegs) then
|
||||
begin
|
||||
{ We can remove the original MOV }
|
||||
DebugMsg(SPeepholeOptimization + 'Mov2Nop 3b done',p);
|
||||
@ -2849,7 +3079,7 @@ unit aoptx86;
|
||||
hp3 := hp2;
|
||||
Continue;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user