diff --git a/rtl/mips/mathu.inc b/rtl/mips/mathu.inc
index f67b40bf72..8b3063dfa6 100644
--- a/rtl/mips/mathu.inc
+++ b/rtl/mips/mathu.inc
@@ -27,6 +27,8 @@ const
   default_fpu_enable = fpu_enable_div_zero or fpu_enable_invalid;
 
   fpu_flags_mask = $7C;
+  fpu_cause_mask = $3F000;
+
   { FPU rounding mask and values }
   fpu_rounding_mask    = $3;
   fpu_rounding_nearest = 0;
@@ -166,6 +168,9 @@ function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
     else
       fsr:=fsr or (fpu_enable_inexact);
 
+    { Reset flags and cause }
+    fsr := fsr and not (fpu_flags_mask or fpu_cause_mask);
+
     { update control register contents }
     set_fsr(fsr);
 
@@ -175,6 +180,6 @@ function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
 
 procedure ClearExceptions(RaisePending: Boolean =true);
   begin
-    set_fsr(get_fsr and $fffffc1f);
+    set_fsr(get_fsr and not (fpu_flags_mask or fpu_cause_mask));
   end;
 
diff --git a/rtl/mips/mips.inc b/rtl/mips/mips.inc
index a8306c50f8..f0d839c164 100644
--- a/rtl/mips/mips.inc
+++ b/rtl/mips/mips.inc
@@ -48,6 +48,8 @@ const
   default_fpu_enable = fpu_enable_div_zero or fpu_enable_invalid;
 
   fpu_flags_mask = $7C;
+  fpu_cause_mask = $3F000;
+
   { FPU rounding mask and values }
   fpu_rounding_mask    = $3;
   fpu_rounding_nearest = 0;
@@ -67,8 +69,8 @@ var
         { enable div by 0 and invalid operation fpu exceptions,
           disable the other exceptions }
         tmp32 := (tmp32 and not fpu_enable_mask) or default_fpu_enable;
-        { Reset flags }
-        tmp32 := tmp32 and not fpu_flags_mask;
+        { Reset flags and cause }
+        tmp32 := tmp32 and not (fpu_flags_mask or fpu_cause_mask);
 
         { round towards nearest; ieee compliant arithmetics }
         tmp32 := (tmp32 and not fpu_rounding_mask) or fpu_rounding_nearest;