diff --git a/.gitattributes b/.gitattributes index 8e37c881d4..2b1ef0f496 100644 --- a/.gitattributes +++ b/.gitattributes @@ -7543,7 +7543,9 @@ rtl/darwin/x86_64/sighnd.inc svneol=native#text/plain rtl/embedded/Makefile svneol=native#text/plain rtl/embedded/Makefile.fpc svneol=native#text/plain rtl/embedded/arm/at91sam7x256.pp svneol=native#text/plain +rtl/embedded/arm/cortexm3.pp svneol=native#text/pascal rtl/embedded/arm/cortexm3_start.inc svneol=native#text/pascal +rtl/embedded/arm/cortexm4.pp svneol=native#text/pascal rtl/embedded/arm/cortexm4f_start.inc svneol=native#text/pascal rtl/embedded/arm/lm3fury.pp svneol=native#text/pascal rtl/embedded/arm/lm3tempest.pp svneol=native#text/pascal @@ -7557,6 +7559,7 @@ rtl/embedded/arm/stm32f10x_hd.pp svneol=native#text/pascal rtl/embedded/arm/stm32f10x_ld.pp svneol=native#text/pascal rtl/embedded/arm/stm32f10x_md.pp svneol=native#text/pascal rtl/embedded/arm/stm32f10x_xl.pp svneol=native#text/pascal +rtl/embedded/arm/xmc4500.pp svneol=native#text/pascal rtl/embedded/avr/atmega128.pp svneol=native#text/plain rtl/embedded/avr/start.inc svneol=native#text/plain rtl/embedded/buildrtl.lpi svneol=native#text/plain diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas index da98706f09..24907f692a 100644 --- a/compiler/arm/aasmcpu.pas +++ b/compiler/arm/aasmcpu.pas @@ -1071,7 +1071,7 @@ implementation curtai:=tai(curtai.next); end; { align thumb in thumb .text section to 4 bytes } - if not(curdata.empty) and (current_settings.cputype in cpu_thumb) then + if not(curdata.empty) and (current_settings.cputype in cpu_thumb+cpu_thumb2) then curdata.Insert(tai_align.Create(4)); list.concatlist(curdata); curdata.free; diff --git a/compiler/arm/cpuinfo.pas b/compiler/arm/cpuinfo.pas index f615ba6f69..26c5fb85a1 100644 --- a/compiler/arm/cpuinfo.pas +++ b/compiler/arm/cpuinfo.pas @@ -90,7 +90,7 @@ Type ct_at91sam7se256, ct_at91sam7x256, ct_at91sam7xc256, - + { STMicroelectronics } ct_stm32f100x4, // LD&MD value line, 4=16,6=32,8=64,b=128 ct_stm32f100x6, @@ -205,6 +205,12 @@ Type { SAMSUNG } ct_sc32442b, + + { Infineon } + ct_xmc4500x1024, + ct_xmc4500x768, + ct_xmc4502x768, + ct_xmc4504x512, // generic Thumb2 target ct_thumb2bare @@ -275,807 +281,147 @@ Const {$WARN 3177 OFF} embedded_controllers : array [tcontrollertype] of tcontrollerdatatype = - (( - controllertypestr:''; - controllerunitstr:''; - flashbase:0; - flashsize:0; - srambase:0; - sramsize:0 - ), + ( + (controllertypestr:''; controllerunitstr:''; flashbase:0; flashsize:0; srambase:0; sramsize:0), + + (controllertypestr:'LPC1343'; controllerunitstr:'LPC1343'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000), + (controllertypestr:'LPC2114'; controllerunitstr:'LPC21x4'; flashbase:$00000000; flashsize:$00040000; srambase:$40000000; sramsize:$00004000), + (controllertypestr:'LPC2124'; controllerunitstr:'LPC21x4'; flashbase:$00000000; flashsize:$00040000; srambase:$40000000; sramsize:$00004000), + (controllertypestr:'LPC2194'; controllerunitstr:'LPC21x4'; flashbase:$00000000; flashsize:$00040000; srambase:$40000000; sramsize:$00004000), + (controllertypestr:'LPC1754'; controllerunitstr:'LPC1754'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00004000), + (controllertypestr:'LPC1756'; controllerunitstr:'LPC1756'; flashbase:$00000000; flashsize:$00040000; srambase:$10000000; sramsize:$00004000), + (controllertypestr:'LPC1758'; controllerunitstr:'LPC1758'; flashbase:$00000000; flashsize:$00080000; srambase:$10000000; sramsize:$00008000), + (controllertypestr:'LPC1764'; controllerunitstr:'LPC1764'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00004000), + (controllertypestr:'LPC1766'; controllerunitstr:'LPC1766'; flashbase:$00000000; flashsize:$00040000; srambase:$10000000; sramsize:$00008000), + (controllertypestr:'LPC1768'; controllerunitstr:'LPC1768'; flashbase:$00000000; flashsize:$00080000; srambase:$10000000; sramsize:$00008000), - ( - controllertypestr:'LPC1343'; - controllerunitstr:'LPC1343'; - flashbase:$00000000; - flashsize:$00008000; - srambase:$10000000; - sramsize:$00002000 - ), - - ( - controllertypestr:'LPC2114'; - controllerunitstr:'LPC21x4'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$40000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC2124'; - controllerunitstr:'LPC21x4'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$40000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC2194'; - controllerunitstr:'LPC21x4'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$40000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC1754'; - controllerunitstr:'LPC1754'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$10000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC1756'; - controllerunitstr:'LPC1756'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$10000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC1758'; - controllerunitstr:'LPC1758'; - flashbase:$00000000; - flashsize:$00080000; - srambase:$10000000; - sramsize:$00008000 - ), - - ( - controllertypestr:'LPC1764'; - controllerunitstr:'LPC1764'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$10000000; - sramsize:$00004000 - ), - - ( - controllertypestr:'LPC1766'; - controllerunitstr:'LPC1766'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$10000000; - sramsize:$00008000 - ), - - ( - controllertypestr:'LPC1768'; - controllerunitstr:'LPC1768'; - flashbase:$00000000; - flashsize:$00080000; - srambase:$10000000; - sramsize:$00008000 - ), - - ( - controllertypestr:'AT91SAM7S256'; - controllerunitstr:'AT91SAM7x256'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$00200000; - sramsize:$00010000 - ), - - ( - controllertypestr:'AT91SAM7SE256'; - controllerunitstr:'AT91SAM7x256'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$00200000; - sramsize:$00010000 - ), - - ( - controllertypestr:'AT91SAM7X256'; - controllerunitstr:'AT91SAM7x256'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$00200000; - sramsize:$00010000 - ), - - ( - controllertypestr:'AT91SAM7XC256'; - controllerunitstr:'AT91SAM7x256'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$00200000; - sramsize:$00010000 - ), + { AT91 } + (controllertypestr:'AT91SAM7S256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000), + (controllertypestr:'AT91SAM7SE256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000), + (controllertypestr:'AT91SAM7X256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000), + (controllertypestr:'AT91SAM7XC256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000), { STM32F1 series } - (controllertypestr:'STM32F100X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), - (controllertypestr:'STM32F100X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000), - (controllertypestr:'STM32F100X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000), - (controllertypestr:'STM32F100XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00002000), - (controllertypestr:'STM32F100XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00006000), - (controllertypestr:'STM32F100XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00008000), - (controllertypestr:'STM32F100XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00008000), - (controllertypestr:'STM32F101X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), - (controllertypestr:'STM32F101X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800), - (controllertypestr:'STM32F101X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800), - (controllertypestr:'STM32F101XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000), - (controllertypestr:'STM32F101XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000), - (controllertypestr:'STM32F101XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$0000C000), - (controllertypestr:'STM32F101XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$0000C000), - (controllertypestr:'STM32F101XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00014000), - (controllertypestr:'STM32F101XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00014000), - (controllertypestr:'STM32F102X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), - (controllertypestr:'STM32F102X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800), - (controllertypestr:'STM32F102X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800), - (controllertypestr:'STM32F102XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000), - (controllertypestr:'STM32F103X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), - (controllertypestr:'STM32F103X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800), - (controllertypestr:'STM32F103X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00005000), - (controllertypestr:'STM32F103XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00005000), - (controllertypestr:'STM32F103XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$0000C000), - (controllertypestr:'STM32F103XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00010000), - (controllertypestr:'STM32F103XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000), - (controllertypestr:'STM32F103XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00018000), - (controllertypestr:'STM32F103XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00018000), - (controllertypestr:'STM32F107X8'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000), - (controllertypestr:'STM32F107XB'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000), - (controllertypestr:'STM32F107XC'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'STM32F100X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), + (controllertypestr:'STM32F100X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000), + (controllertypestr:'STM32F100X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000), + (controllertypestr:'STM32F100XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00002000), + (controllertypestr:'STM32F100XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00006000), + (controllertypestr:'STM32F100XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'STM32F100XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'STM32F101X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), + (controllertypestr:'STM32F101X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800), + (controllertypestr:'STM32F101X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800), + (controllertypestr:'STM32F101XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'STM32F101XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'STM32F101XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$0000C000), + (controllertypestr:'STM32F101XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$0000C000), + (controllertypestr:'STM32F101XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00014000), + (controllertypestr:'STM32F101XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00014000), + (controllertypestr:'STM32F102X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), + (controllertypestr:'STM32F102X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800), + (controllertypestr:'STM32F102X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800), + (controllertypestr:'STM32F102XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'STM32F103X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000), + (controllertypestr:'STM32F103X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800), + (controllertypestr:'STM32F103X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00005000), + (controllertypestr:'STM32F103XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00005000), + (controllertypestr:'STM32F103XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$0000C000), + (controllertypestr:'STM32F103XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'STM32F103XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'STM32F103XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'STM32F103XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'STM32F107X8'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'STM32F107XB'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'STM32F107XC'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), - { TI - 64 K Flash, 16 K SRAM Devices } - // ct_lm3s1110, - ( - controllertypestr:'LM3S1110'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1133, - ( - controllertypestr:'LM3S1133'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1138, - ( - controllertypestr:'LM3S1138'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1150, - ( - controllertypestr:'LM3S1150'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1162, - ( - controllertypestr:'LM3S1162'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1165, - ( - controllertypestr:'LM3S1165'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s1166, - ( - controllertypestr:'LM3S1166'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s2110, - ( - controllertypestr:'LM3S2110'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s2139, - ( - controllertypestr:'LM3S2139'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s6100, - ( - controllertypestr:'LM3S6100'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), - // ct_lm3s6110, - ( - controllertypestr:'LM3S6110'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00010000; - srambase:$20000000; - sramsize:$00004000 - ), + (controllertypestr:'LM3S1110'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1133'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1138'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1150'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1162'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1165'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S1166'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S2110'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S2139'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S6100'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), + (controllertypestr:'LM3S6110'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000), - { TI - 128K Flash, 32K SRAM devices } - // ct_lm3s1601, - ( - controllertypestr:'LM3S1601'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1608, - ( - controllertypestr:'LM3S1608'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1620, - ( - controllertypestr:'LM3S1620'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1635, - ( - controllertypestr:'LM3S1635'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1636, - ( - controllertypestr:'LM3S1636'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1637, - ( - controllertypestr:'LM3S1637'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s1651, - ( - controllertypestr:'LM3S1651'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s2601, - ( - controllertypestr:'LM3S2601'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s2608, - ( - controllertypestr:'LM3S2608'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s2620, - ( - controllertypestr:'LM3S2620'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s2637, - ( - controllertypestr:'LM3S2637'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s2651, - ( - controllertypestr:'LM3S2651'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s6610, - ( - controllertypestr:'LM3S6610'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s6611, - ( - controllertypestr:'LM3S6611'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s6618, - ( - controllertypestr:'LM3S6618'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s6633, - ( - controllertypestr:'LM3S6633'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s6637, - ( - controllertypestr:'LM3S6637'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), - // ct_lm3s8630, - ( - controllertypestr:'LM3S8630'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00020000; - srambase:$20000000; - sramsize:$00008000 - ), + { TI - 128K Flash, 32K SRAM devices } + (controllertypestr:'LM3S1601'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1608'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1620'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1635'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1636'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1637'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S1651'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S2601'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S2608'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S2620'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S2637'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S2651'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S6610'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S6611'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S6618'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S6633'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S6637'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), + (controllertypestr:'LM3S8630'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00008000), - { TI - 256K Flash, 64K SRAM devices } - // ct_lm3s1911, - ( - controllertypestr:'LM3S1911'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1918, - ( - controllertypestr:'LM3S1918'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1937, - ( - controllertypestr:'LM3S1937'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1958, - ( - controllertypestr:'LM3S1958'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1960, - ( - controllertypestr:'LM3S1960'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1968, - ( - controllertypestr:'LM3S1968'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1969, - ( - controllertypestr:'LM3S1969'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2911, - ( - controllertypestr:'LM3S2911'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2918, - ( - controllertypestr:'LM3S2918'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2919, - ( - controllertypestr:'LM3S2919'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2939, - ( - controllertypestr:'LM3S2939'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2948, - ( - controllertypestr:'LM3S2948'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2950, - ( - controllertypestr:'LM3S2950'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s2965, - ( - controllertypestr:'LM3S2965'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6911, - ( - controllertypestr:'LM3S6911'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6918, - ( - controllertypestr:'LM3S6918'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6938, - ( - controllertypestr:'LM3S6938'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6950, - ( - controllertypestr:'LM3S6950'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6952, - ( - controllertypestr:'LM3S6952'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s6965, - ( - controllertypestr:'LM3S6965'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8930, - ( - controllertypestr:'LM3S8930'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8933, - ( - controllertypestr:'LM3S8933'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8938, - ( - controllertypestr:'LM3S8938'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8962, - ( - controllertypestr:'LM3S8962'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8970, - ( - controllertypestr:'LM3S8970'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s8971, - ( - controllertypestr:'LM3S8971'; - controllerunitstr:'LM3FURY'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), + { TI - 256K Flash, 64K SRAM devices } + (controllertypestr:'LM3S1911'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1918'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1937'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1958'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1960'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1968'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1969'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2911'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2918'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2919'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2939'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2948'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2950'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S2965'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6911'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6918'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6938'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6950'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6952'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S6965'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8930'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8933'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8938'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8962'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8970'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S8971'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), - { TI - Tempest parts - up to 512 K Flash, 96 K SRAM } - // ct_lm3s5951, - ( - controllertypestr:'LM3S5951'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s5956, - ( - controllertypestr:'LM3S5956'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00010000 - ), - // ct_lm3s1b21, - ( - controllertypestr:'LM3S1B21'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s2b93, - ( - controllertypestr:'LM3S2B93'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s5b91, - ( - controllertypestr:'LM3S5B91'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s9b81, - ( - controllertypestr:'LM3S9B81'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s9b90, - ( - controllertypestr:'LM3S9B90'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s9b92, - ( - controllertypestr:'LM3S9B92'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s9b95, - ( - controllertypestr:'LM3S9B95'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - // ct_lm3s9b96, - ( - controllertypestr:'LM3S9B96'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00018000 - ), - - // ct_lm3s5d51, - ( - controllertypestr:'LM3S5D51'; - controllerunitstr:'LM3TEMPEST'; - flashbase:$00000000; - flashsize:$00080000; - srambase:$20000000; - sramsize:$00018000 - ), - - // ct_lm4f120h5, - ( - controllertypestr:'LM4F120H5'; - controllerunitstr:'LM4F120'; - flashbase:$00000000; - flashsize:$00040000; - srambase:$20000000; - sramsize:$00008000 - ), - - //ct_SC32442b, - ( - controllertypestr:'SC32442B'; - controllerunitstr:'sc32442b'; - flashbase:$00000000; - flashsize:$00000000; - srambase:$00000000; - sramsize:$08000000 - ), - - // bare bones Thumb2 - ( - controllertypestr:'THUMB2_BARE'; - controllerunitstr:'THUMB2_BARE'; - flashbase:$00000000; - flashsize:$00002000; - srambase:$20000000; - sramsize:$00000400 - ) + { TI - Tempest parts - up to 512 K Flash, 96 K SRAM } + (controllertypestr:'LM3S5951'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S5956'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'LM3S1B21'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S2B93'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S5B91'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S9B81'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S9B90'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S9B92'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S9B95'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S9B96'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00018000), + (controllertypestr:'LM3S5D51'; controllerunitstr:'LM3TEMPEST'; flashbase:$00000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000), + + { TI } + (controllertypestr:'LM4F120H5'; controllerunitstr:'LM4F120'; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000), + + { Samsung } + (controllertypestr:'SC32442B'; controllerunitstr:'SC32442b'; flashbase:$00000000; flashsize:$00000000; srambase:$00000000; sramsize:$08000000), + + { Infinion } + (controllertypestr:'XMC4500X1024'; controllerunitstr:'XMC4500'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'XMC4500X768'; controllerunitstr:'XMC4500'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'XMC4502X768'; controllerunitstr:'XMC4502'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00010000), + (controllertypestr:'XMC4504X512'; controllerunitstr:'XMC4504'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000), + + { Bare bones } + (controllertypestr:'THUMB2_BARE'; controllerunitstr:'THUMB2_BARE'; flashbase:$00000000; flashsize:$00002000; srambase:$20000000; sramsize:$00000400) ); vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16]; diff --git a/compiler/systems/t_embed.pas b/compiler/systems/t_embed.pas index 6668027bc1..5458bd5282 100644 --- a/compiler/systems/t_embed.pas +++ b/compiler/systems/t_embed.pas @@ -344,6 +344,12 @@ begin { TI - Stellaris something } ct_lm4f120h5, + { Infineon } + ct_xmc4500x1024, + ct_xmc4500x768, + ct_xmc4502x768, + ct_xmc4504x512, + ct_sc32442b, ct_thumb2bare: begin @@ -379,6 +385,7 @@ begin Add('{'); Add(' .text :'); Add(' {'); + Add(' _text_start = .;'); Add(' KEEP(*(.init, .init.*))'); Add(' *(.text, .text.*)'); Add(' *(.strings)'); diff --git a/rtl/embedded/Makefile b/rtl/embedded/Makefile index 3534a4a4c9..2989dc1c63 100644 --- a/rtl/embedded/Makefile +++ b/rtl/embedded/Makefile @@ -1,5 +1,5 @@ # -# Don't edit, this file is generated by FPCMake Version 2.0.0 [2013/03/09] +# Don't edit, this file is generated by FPCMake Version 2.0.0 [2013/03/10] # default: all MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-qnx i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android m68k-linux m68k-freebsd m68k-netbsd m68k-amiga m68k-atari m68k-openbsd m68k-palmos m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macos powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded arm-linux arm-palmos arm-darwin arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux jvm-java jvm-android @@ -334,10 +334,10 @@ CPU_SPECIFIC_COMMON_UNITS= ifeq ($(ARCH),arm) CPU_SPECIFIC_COMMON_UNITS=sysutils sysconst ifeq ($(SUBARCH),armv7m) -CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1343 lpc1768 lm4f120 # thumb2_bare +CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1343 lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare endif ifeq ($(SUBARCH),armv7em) -CPU_UNITS=lm4f120 # thumb2_bare +CPU_UNITS=lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare endif ifeq ($(SUBARCH),armv4t) CPU_UNITS=lpc21x4 at91sam7x256 sc32442b diff --git a/rtl/embedded/Makefile.fpc b/rtl/embedded/Makefile.fpc index e99337da2f..4f9200d61f 100644 --- a/rtl/embedded/Makefile.fpc +++ b/rtl/embedded/Makefile.fpc @@ -54,10 +54,10 @@ CPU_SPECIFIC_COMMON_UNITS= ifeq ($(ARCH),arm) CPU_SPECIFIC_COMMON_UNITS=sysutils sysconst ifeq ($(SUBARCH),armv7m) -CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1343 lpc1768 lm4f120 # thumb2_bare +CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1343 lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare endif ifeq ($(SUBARCH),armv7em) -CPU_UNITS=lm4f120 # thumb2_bare +CPU_UNITS=lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare endif ifeq ($(SUBARCH),armv4t) CPU_UNITS=lpc21x4 at91sam7x256 sc32442b diff --git a/rtl/embedded/arm/cortexm3.pp b/rtl/embedded/arm/cortexm3.pp new file mode 100644 index 0000000000..9fa76d4cfa --- /dev/null +++ b/rtl/embedded/arm/cortexm3.pp @@ -0,0 +1,189 @@ +{ + System register definitions and utility code for Cortex-M3 + + Created by Jeppe Johansen 2012 - jeppe@j-software.dk +} +unit cortexm3; + +interface + +{$PACKRECORDS 2} +const + SCS_BASE = $E000E000; + DWT_BASE = $E0001000; + FP_BASE = $E0002000; + ITM_BASE = $E0000000; + TPIU_BASE = $E0040000; + ETM_BASE = $E0041000; + +type + + TNVICRegisters = record + ISER: array[0..7] of longword; + reserved0: array[0..23] of longword; + ICER: array[0..7] of longword; + reserved1: array[0..23] of longword; + ISPR: array[0..7] of longword; + reserved2: array[0..23] of longword; + ICPR: array[0..7] of longword; + reserved3: array[0..23] of longword; + IABR: array[0..7] of longword; + reserved4: array[0..55] of longword; + IP: array[0..239] of byte; + reserved5: array[0..643] of longword; + STIR: longword; + end; + + TSCBRegisters = record + CPUID, {!< CPU ID Base Register } + ICSR, {!< Interrupt Control State Register } + VTOR, {!< Vector Table Offset Register } + AIRCR, {!< Application Interrupt / Reset Control Register } + SCR, {!< System Control Register } + CCR: longword; {!< Configuration Control Register } + SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } + SHCSR, {!< System Handler Control and State Register } + CFSR, {!< Configurable Fault Status Register } + HFSR, {!< Hard Fault Status Register } + DFSR, {!< Debug Fault Status Register } + MMFAR, {!< Mem Manage Address Register } + BFAR, {!< Bus Fault Address Register } + AFSR: longword; {!< Auxiliary Fault Status Register } + PFR: array[0..1] of longword; {!< Processor Feature Register } + DFR, {!< Debug Feature Register } + ADR: longword; {!< Auxiliary Feature Register } + MMFR: array[0..3] of longword; {!< Memory Model Feature Register } + ISAR: array[0..4] of longword; {!< ISA Feature Register } + end; + + TSysTickRegisters = record + Ctrl, + Load, + Val, + Calib: longword; + end; + + TIDRegisters = record + PID4_7: array[0..3] of longword; + PID0_3: array[0..3] of longword; + CID: array[0..3] of longword; + end; + + TCoreDebugRegisters = record + DHCSR, + DCRSR, + DCRDR, + DEMCR: longword; + end; + + TFPRegisters = record + Ctrl, + Remap: longword; + Comp: array[0..7] of longword; + res: array[0..987] of longword; + ID: TIDRegisters; + end; + + TDWTEntry = record + Comp, + Mask, + Func, + res: longword; + end; + + TDWTRegisters = record + Ctrl, + CycCnt, + CPICnt, + ExcCnt, + SleepCnt, + LSUCnt, + FoldCnt, + PCSR: longword; + Entries: array[0..3] of TDWTEntry; + end; + + TITMRegisters = record + Stimulus: array[0..31] of longword; + res0: array[0..($E00-$7C-4)-1] of byte; + TraceEnable: longword; + res1: array[0..($E40-$E00-4)-1] of byte; + TracePrivilege: longword; + res2: array[0..($E80-$E40-4)-1] of byte; + TraceControl: longword; + res3: array[0..($EF8-$E80-4)-1] of byte; + IntegrationWrite, + IntegrationRead, + IntegrationModeCtrl: longword; + res4: array[0..($FB0-$F00-4)-1] of byte; + LockAccess, + LockStatus: longword; + res5: array[0..($FD0-$FB4-4)-1] of byte; + ID: TIDRegisters; + end; + + TTPIURegisters = record + SupportedSyncPortSizes, + CurrentSyncPortSize: longword; + res0: array[0..($10-$04-4)-1] of byte; + AsyncColckPrescaler: longword; + res1: array[0..($F0-$10-4)-1] of byte; + SelectedPinProtocol: longword; + res2: array[0..($100-$F0-4)-1] of byte; + TriggerControl: array[0..2] of longword; + res3: array[0..($200-$108-4)-1] of byte; + TestPattern: array[0..2] of longword; + res4: array[0..($300-$208-4)-1] of byte; + FormatFlushStatus, + FormatControl, + FormatSyncCounter: longword; + res5: array[0..($EF0-$308-4)-1] of byte; + ITATBCTR2: longword; + res6: longword; + ITATBCTR0: longword; + end; + +var + // System Control + InterruptControlType: longword absolute (SCS_BASE+$0004); + SCB: TSCBRegisters absolute (SCS_BASE+$0D00); + SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); + NVIC: TNVICRegisters absolute (SCS_BASE+$0100); + SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000); + SCBID: TIDRegisters absolute (SCS_BASE+$EFD0); + + // Core Debug + CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0); + + // Flash Patch + FP: TFPRegisters absolute FP_BASE; + + DWT: TDWTRegisters absolute DWT_BASE; + + ITM: TITMRegisters absolute ITM_BASE; + + TPIU: TTPIURegisters absolute TPIU_BASE; + +type + TITM_Port = 0..31; + +procedure ITM_SendData(Port: TITM_Port; Data: longword); inline; + +implementation + +const + CoreDebug_DEMCR_TRCENA = $01000000; + ITM_TCR_ITMENA = $00000001; + +procedure ITM_SendData(Port: TITM_Port; Data: longword); +begin + if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and + ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and + ((ITM.TraceEnable and (1 shl Port)) <> 0) then + begin + while ITM.Stimulus[Port] = 0 do; + ITM.Stimulus[Port] := Data; + end; +end; + +end. diff --git a/rtl/embedded/arm/cortexm3_start.inc b/rtl/embedded/arm/cortexm3_start.inc index 415aab73dd..82202b1565 100644 --- a/rtl/embedded/arm/cortexm3_start.inc +++ b/rtl/embedded/arm/cortexm3_start.inc @@ -2,6 +2,7 @@ var _stack_top: record end; external name '_stack_top'; _data: record end; external name '_data'; _edata: record end; external name '_edata'; + _text_start: record end; external name '_text_start'; _etext: record end; external name '_etext'; _bss_start: record end; external name '_bss_start'; _bss_end: record end; external name '_bss_end'; @@ -36,6 +37,12 @@ asm strls r0,[r1],#4 bls .Lzeroloop +{$ifdef REMAP_VECTTAB} + ldr r0, .Lvtor + ldr r1, .Ltext_start + str r1, [r0] +{$endif REMAP_VECTTAB} + bl PASCALMAIN b HaltProc @@ -49,4 +56,10 @@ asm .long _data .L_edata: .long _edata +{$ifdef REMAP_VECTTAB} +.Lvtor: + .long 0xE000ED08 +.Ltext_start: + .long _text_start +{$endif REMAP_VECTTAB} end; \ No newline at end of file diff --git a/rtl/embedded/arm/cortexm4.pp b/rtl/embedded/arm/cortexm4.pp new file mode 100644 index 0000000000..aa4685b249 --- /dev/null +++ b/rtl/embedded/arm/cortexm4.pp @@ -0,0 +1,189 @@ +{ + System register definitions and utility code for Cortex-M4 + + Created by Jeppe Johansen 2012 - jeppe@j-software.dk +} +unit cortexm4; + +interface + +{$PACKRECORDS 2} +const + SCS_BASE = $E000E000; + DWT_BASE = $E0001000; + FP_BASE = $E0002000; + ITM_BASE = $E0000000; + TPIU_BASE = $E0040000; + ETM_BASE = $E0041000; + +type + + TNVICRegisters = record + ISER: array[0..7] of longword; + reserved0: array[0..23] of longword; + ICER: array[0..7] of longword; + reserved1: array[0..23] of longword; + ISPR: array[0..7] of longword; + reserved2: array[0..23] of longword; + ICPR: array[0..7] of longword; + reserved3: array[0..23] of longword; + IABR: array[0..7] of longword; + reserved4: array[0..55] of longword; + IP: array[0..239] of byte; + reserved5: array[0..643] of longword; + STIR: longword; + end; + + TSCBRegisters = record + CPUID, {!< CPU ID Base Register } + ICSR, {!< Interrupt Control State Register } + VTOR, {!< Vector Table Offset Register } + AIRCR, {!< Application Interrupt / Reset Control Register } + SCR, {!< System Control Register } + CCR: longword; {!< Configuration Control Register } + SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } + SHCSR, {!< System Handler Control and State Register } + CFSR, {!< Configurable Fault Status Register } + HFSR, {!< Hard Fault Status Register } + DFSR, {!< Debug Fault Status Register } + MMFAR, {!< Mem Manage Address Register } + BFAR, {!< Bus Fault Address Register } + AFSR: longword; {!< Auxiliary Fault Status Register } + PFR: array[0..1] of longword; {!< Processor Feature Register } + DFR, {!< Debug Feature Register } + ADR: longword; {!< Auxiliary Feature Register } + MMFR: array[0..3] of longword; {!< Memory Model Feature Register } + ISAR: array[0..4] of longword; {!< ISA Feature Register } + end; + + TSysTickRegisters = record + Ctrl, + Load, + Val, + Calib: longword; + end; + + TIDRegisters = record + PID4_7: array[0..3] of longword; + PID0_3: array[0..3] of longword; + CID: array[0..3] of longword; + end; + + TCoreDebugRegisters = record + DHCSR, + DCRSR, + DCRDR, + DEMCR: longword; + end; + + TFPRegisters = record + Ctrl, + Remap: longword; + Comp: array[0..7] of longword; + res: array[0..987] of longword; + ID: TIDRegisters; + end; + + TDWTEntry = record + Comp, + Mask, + Func, + res: longword; + end; + + TDWTRegisters = record + Ctrl, + CycCnt, + CPICnt, + ExcCnt, + SleepCnt, + LSUCnt, + FoldCnt, + PCSR: longword; + Entries: array[0..3] of TDWTEntry; + end; + + TITMRegisters = record + Stimulus: array[0..31] of longword; + res0: array[0..($E00-$7C-4)-1] of byte; + TraceEnable: longword; + res1: array[0..($E40-$E00-4)-1] of byte; + TracePrivilege: longword; + res2: array[0..($E80-$E40-4)-1] of byte; + TraceControl: longword; + res3: array[0..($EF8-$E80-4)-1] of byte; + IntegrationWrite, + IntegrationRead, + IntegrationModeCtrl: longword; + res4: array[0..($FB0-$F00-4)-1] of byte; + LockAccess, + LockStatus: longword; + res5: array[0..($FD0-$FB4-4)-1] of byte; + ID: TIDRegisters; + end; + + TTPIURegisters = record + SupportedSyncPortSizes, + CurrentSyncPortSize: longword; + res0: array[0..($10-$04-4)-1] of byte; + AsyncColckPrescaler: longword; + res1: array[0..($F0-$10-4)-1] of byte; + SelectedPinProtocol: longword; + res2: array[0..($100-$F0-4)-1] of byte; + TriggerControl: array[0..2] of longword; + res3: array[0..($200-$108-4)-1] of byte; + TestPattern: array[0..2] of longword; + res4: array[0..($300-$208-4)-1] of byte; + FormatFlushStatus, + FormatControl, + FormatSyncCounter: longword; + res5: array[0..($EF0-$308-4)-1] of byte; + ITATBCTR2: longword; + res6: longword; + ITATBCTR0: longword; + end; + +var + // System Control + InterruptControlType: longword absolute (SCS_BASE+$0004); + SCB: TSCBRegisters absolute (SCS_BASE+$0D00); + SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); + NVIC: TNVICRegisters absolute (SCS_BASE+$0100); + SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000); + SCBID: TIDRegisters absolute (SCS_BASE+$EFD0); + + // Core Debug + CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0); + + // Flash Patch + FP: TFPRegisters absolute FP_BASE; + + DWT: TDWTRegisters absolute DWT_BASE; + + ITM: TITMRegisters absolute ITM_BASE; + + TPIU: TTPIURegisters absolute TPIU_BASE; + +type + TITM_Port = 0..31; + +procedure ITM_SendData(Port: TITM_Port; Data: longword); inline; + +implementation + +const + CoreDebug_DEMCR_TRCENA = $01000000; + ITM_TCR_ITMENA = $00000001; + +procedure ITM_SendData(Port: TITM_Port; Data: longword); +begin + if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and + ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and + ((ITM.TraceEnable and (1 shl Port)) <> 0) then + begin + while ITM.Stimulus[Port] = 0 do; + ITM.Stimulus[Port] := Data; + end; +end; + +end. diff --git a/rtl/embedded/arm/cortexm4f_start.inc b/rtl/embedded/arm/cortexm4f_start.inc index 415aab73dd..82202b1565 100644 --- a/rtl/embedded/arm/cortexm4f_start.inc +++ b/rtl/embedded/arm/cortexm4f_start.inc @@ -2,6 +2,7 @@ var _stack_top: record end; external name '_stack_top'; _data: record end; external name '_data'; _edata: record end; external name '_edata'; + _text_start: record end; external name '_text_start'; _etext: record end; external name '_etext'; _bss_start: record end; external name '_bss_start'; _bss_end: record end; external name '_bss_end'; @@ -36,6 +37,12 @@ asm strls r0,[r1],#4 bls .Lzeroloop +{$ifdef REMAP_VECTTAB} + ldr r0, .Lvtor + ldr r1, .Ltext_start + str r1, [r0] +{$endif REMAP_VECTTAB} + bl PASCALMAIN b HaltProc @@ -49,4 +56,10 @@ asm .long _data .L_edata: .long _edata +{$ifdef REMAP_VECTTAB} +.Lvtor: + .long 0xE000ED08 +.Ltext_start: + .long _text_start +{$endif REMAP_VECTTAB} end; \ No newline at end of file diff --git a/rtl/embedded/arm/lm4f120.pp b/rtl/embedded/arm/lm4f120.pp index ee922ffec5..9800f3aba0 100644 --- a/rtl/embedded/arm/lm4f120.pp +++ b/rtl/embedded/arm/lm4f120.pp @@ -360,81 +360,81 @@ interrupt_vectors: .weak Timer_3264_5B_interrupt .weak System_Exception_imprecise_interrupt - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set GPIO_Port_A_interrupt, Startup - .set GPIO_Port_B_interrupt, Startup - .set GPIO_Port_C_interrupt, Startup - .set GPIO_Port_D_interrupt, Startup - .set GPIO_Port_E_interrupt, Startup - .set UART0_interrupt, Startup - .set UART1_interrupt, Startup - .set SSI0_interrupt, Startup - .set I2C0_interrupt, Startup - .set ADC0_Seq_0_interrupt, Startup - .set ADC0_Seq_1_interrupt, Startup - .set ADC0_Seq_2_interrupt, Startup - .set ADC0_Seq_3_interrupt, Startup - .set Watchdog_0_and_1_interrupt, Startup - .set Timer_1632_0A_interrupt, Startup - .set Timer_1632_0B_interrupt, Startup - .set Timer_1632_1A_interrupt, Startup - .set Timer_1632_1B_interrupt, Startup - .set Timer_1632_2A_interrupt, Startup - .set Timer_1632_2B_interrupt, Startup - .set Analog_Comp_0_interrupt, Startup - .set Analog_Comp_1_interrupt, Startup - .set System_Control_interrupt, Startup - .set Flash_and_EEPROM_interrupt, Startup - .set GPIO_Port_F_interrupt, Startup - .set UART2_interrupt, Startup - .set SSI1_interrupt, Startup - .set Timer_1632_3A_interrupt, Startup - .set Timer_1632_3B_interrupt, Startup - .set I2C1_interrupt, Startup - .set CAN0_interrupt, Startup - .set Hibernation_interrupt, Startup - .set USB_interrupt, Startup - .set uDMA_Software_interrupt, Startup - .set uDMA_Error_interrupt, Startup - .set ADC1_Seq_0_interrupt, Startup - .set ADC1_Seq_1_interrupt, Startup - .set ADC1_Seq_2_interrupt, Startup - .set ADC1_Seq_3_interrupt, Startup - .set SSI2_interrupt, Startup - .set SSI3_interrupt, Startup - .set UART3_interrupt, Startup - .set UART4_interrupt, Startup - .set UART5_interrupt, Startup - .set UART6_interrupt, Startup - .set UART7_interrupt, Startup - .set I2C2_interrupt, Startup - .set I2C3_interrupt, Startup - .set Timer_1632_4A_interrupt, Startup - .set Timer_1632_4B_interrupt, Startup - .set Timer_1632_5A_interrupt, Startup - .set Timer_1632_5B_interrupt, Startup - .set Timer_3264_0A_interrupt, Startup - .set Timer_3264_0B_interrupt, Startup - .set Timer_3264_1A_interrupt, Startup - .set Timer_3264_1B_interrupt, Startup - .set Timer_3264_2A_interrupt, Startup - .set Timer_3264_2B_interrupt, Startup - .set Timer_3264_3A_interrupt, Startup - .set Timer_3264_3B_interrupt, Startup - .set Timer_3264_4A_interrupt, Startup - .set Timer_3264_4B_interrupt, Startup - .set Timer_3264_5A_interrupt, Startup - .set Timer_3264_5B_interrupt, Startup - .set System_Exception_imprecise_interrupt, Startup + .set GPIO_Port_A_interrupt, HaltProc + .set GPIO_Port_B_interrupt, HaltProc + .set GPIO_Port_C_interrupt, HaltProc + .set GPIO_Port_D_interrupt, HaltProc + .set GPIO_Port_E_interrupt, HaltProc + .set UART0_interrupt, HaltProc + .set UART1_interrupt, HaltProc + .set SSI0_interrupt, HaltProc + .set I2C0_interrupt, HaltProc + .set ADC0_Seq_0_interrupt, HaltProc + .set ADC0_Seq_1_interrupt, HaltProc + .set ADC0_Seq_2_interrupt, HaltProc + .set ADC0_Seq_3_interrupt, HaltProc + .set Watchdog_0_and_1_interrupt, HaltProc + .set Timer_1632_0A_interrupt, HaltProc + .set Timer_1632_0B_interrupt, HaltProc + .set Timer_1632_1A_interrupt, HaltProc + .set Timer_1632_1B_interrupt, HaltProc + .set Timer_1632_2A_interrupt, HaltProc + .set Timer_1632_2B_interrupt, HaltProc + .set Analog_Comp_0_interrupt, HaltProc + .set Analog_Comp_1_interrupt, HaltProc + .set System_Control_interrupt, HaltProc + .set Flash_and_EEPROM_interrupt, HaltProc + .set GPIO_Port_F_interrupt, HaltProc + .set UART2_interrupt, HaltProc + .set SSI1_interrupt, HaltProc + .set Timer_1632_3A_interrupt, HaltProc + .set Timer_1632_3B_interrupt, HaltProc + .set I2C1_interrupt, HaltProc + .set CAN0_interrupt, HaltProc + .set Hibernation_interrupt, HaltProc + .set USB_interrupt, HaltProc + .set uDMA_Software_interrupt, HaltProc + .set uDMA_Error_interrupt, HaltProc + .set ADC1_Seq_0_interrupt, HaltProc + .set ADC1_Seq_1_interrupt, HaltProc + .set ADC1_Seq_2_interrupt, HaltProc + .set ADC1_Seq_3_interrupt, HaltProc + .set SSI2_interrupt, HaltProc + .set SSI3_interrupt, HaltProc + .set UART3_interrupt, HaltProc + .set UART4_interrupt, HaltProc + .set UART5_interrupt, HaltProc + .set UART6_interrupt, HaltProc + .set UART7_interrupt, HaltProc + .set I2C2_interrupt, HaltProc + .set I2C3_interrupt, HaltProc + .set Timer_1632_4A_interrupt, HaltProc + .set Timer_1632_4B_interrupt, HaltProc + .set Timer_1632_5A_interrupt, HaltProc + .set Timer_1632_5B_interrupt, HaltProc + .set Timer_3264_0A_interrupt, HaltProc + .set Timer_3264_0B_interrupt, HaltProc + .set Timer_3264_1A_interrupt, HaltProc + .set Timer_3264_1B_interrupt, HaltProc + .set Timer_3264_2A_interrupt, HaltProc + .set Timer_3264_2B_interrupt, HaltProc + .set Timer_3264_3A_interrupt, HaltProc + .set Timer_3264_3B_interrupt, HaltProc + .set Timer_3264_4A_interrupt, HaltProc + .set Timer_3264_4B_interrupt, HaltProc + .set Timer_3264_5A_interrupt, HaltProc + .set Timer_3264_5B_interrupt, HaltProc + .set System_Exception_imprecise_interrupt, HaltProc .text end; diff --git a/rtl/embedded/arm/stm32f10x_conn.pp b/rtl/embedded/arm/stm32f10x_conn.pp index 77a4fb95fb..e8e2c87646 100644 --- a/rtl/embedded/arm/stm32f10x_conn.pp +++ b/rtl/embedded/arm/stm32f10x_conn.pp @@ -23,8 +23,6 @@ const APB2Base = PeripheralBase+$10000; AHBBase = PeripheralBase+$20000; - SCS_BASE = $E000E000; - { FSMC } FSMCBank1NOR1 = FSMCBase+$00000000; FSMCBank1NOR2 = FSMCBase+$04000000; @@ -329,51 +327,6 @@ type WRPR: longword; end; - TNVICRegisters = record - ISER: array[0..7] of longword; - reserved0: array[0..23] of longword; - ICER: array[0..7] of longword; - reserved1: array[0..23] of longword; - ISPR: array[0..7] of longword; - reserved2: array[0..23] of longword; - ICPR: array[0..7] of longword; - reserved3: array[0..23] of longword; - IABR: array[0..7] of longword; - reserved4: array[0..55] of longword; - IP: array[0..239] of byte; - reserved5: array[0..643] of longword; - STIR: longword; - end; - - TSCBRegisters = record - CPUID, {!< CPU ID Base Register } - ICSR, {!< Interrupt Control State Register } - VTOR, {!< Vector Table Offset Register } - AIRCR, {!< Application Interrupt / Reset Control Register } - SCR, {!< System Control Register } - CCR: longword; {!< Configuration Control Register } - SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } - SHCSR, {!< System Handler Control and State Register } - CFSR, {!< Configurable Fault Status Register } - HFSR, {!< Hard Fault Status Register } - DFSR, {!< Debug Fault Status Register } - MMFAR, {!< Mem Manage Address Register } - BFAR, {!< Bus Fault Address Register } - AFSR: longword; {!< Auxiliary Fault Status Register } - PFR: array[0..1] of longword; {!< Processor Feature Register } - DFR, {!< Debug Feature Register } - ADR: longword; {!< Auxiliary Feature Register } - MMFR: array[0..3] of longword; {!< Memory Model Feature Register } - ISAR: array[0..4] of longword; {!< ISA Feature Register } - end; - - TSysTickRegisters = record - Ctrl, - Load, - Val, - Calib: longword; - end; - {$ALIGN 2} var { Timers } @@ -458,15 +411,6 @@ var { CRC } CRC: TCRCRegisters absolute (AHBBase+$3000); - { SCB } - SCB: TSCBRegisters absolute (SCS_BASE+$0D00); - - { SysTick } - SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); - - { NVIC } - NVIC: TNVICRegisters absolute (SCS_BASE+$0100); - implementation procedure NMI_interrupt; external name 'NMI_interrupt'; @@ -706,77 +650,77 @@ interrupt_vectors: .weak USB_On_The_Go_FS_global_interrupt - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set Window_Watchdog_interrupt, Startup - .set PVD_through_EXTI_Line_detection_interrupt, Startup - .set Tamper_interrupt, Startup - .set RTC_global_interrupt, Startup - .set Flash_global_interrupt, Startup - .set RCC_global_interrupt, Startup - .set EXTI_Line0_interrupt, Startup - .set EXTI_Line1_interrupt, Startup - .set EXTI_Line2_interrupt, Startup - .set EXTI_Line3_interrupt, Startup - .set EXTI_Line4_interrupt, Startup - .set DMA1_Channel1_global_interrupt, Startup - .set DMA1_Channel2_global_interrupt, Startup - .set DMA1_Channel3_global_interrupt, Startup - .set DMA1_Channel4_global_interrupt, Startup - .set DMA1_Channel5_global_interrupt, Startup - .set DMA1_Channel6_global_interrupt, Startup - .set DMA1_Channel7_global_interrupt, Startup - .set ADC1_and_ADC2_global_interrupt, Startup - .set CAN1_TX_interrupts, Startup - .set CAN1_RX0_interrupts, Startup - .set CAN1_RX1_interrupt, Startup - .set CAN1_SCE_interrupt, Startup - .set EXTI_Line9_5_interrupts, Startup - .set TIM1_Break_interrupt, Startup - .set TIM1_Update_interrupt, Startup - .set TIM1_Trigger_and_Commutation_interrupts, Startup - .set TIM1_Capture_Compare_interrupt, Startup - .set TIM2_global_interrupt, Startup - .set TIM3_global_interrupt, Startup - .set TIM4_global_interrupt, Startup - .set I2C1_event_interrupt, Startup - .set I2C1_error_interrupt, Startup - .set I2C2_event_interrupt, Startup - .set I2C2_error_interrupt, Startup - .set SPI1_global_interrupt, Startup - .set SPI2_global_interrupt, Startup - .set USART1_global_interrupt, Startup - .set USART2_global_interrupt, Startup - .set USART3_global_interrupt, Startup - .set EXTI_Line15_10_interrupts, Startup - .set RTC_alarm_through_EXTI_line_interrupt, Startup - .set USB_OTG_FS_Wakeup_through_EXTI_line_interrupt, Startup - .set TIM5_global_interrupt, Startup - .set SPI3_global_interrupt, Startup - .set UART4_global_interrupt, Startup - .set UART5_global_interrupt, Startup - .set TIM6_global_interrupt, Startup - .set TIM7_global_interrupt, Startup - .set DMA2_Channel1_global_interrupt, Startup - .set DMA2_Channel2_global_interrupt, Startup - .set DMA2_Channel3_global_interrupt, Startup - .set DMA2_Channel4_global_interrupt, Startup - .set DMA2_Channel5_global_interrupt, Startup - .set Ethernet_global_interrupt, Startup - .set Ethernet_Wakeup_through_EXTI_line_interrupt, Startup - .set CAN2_TX_interrupts, Startup - .set CAN2_RX0_interrupts, Startup - .set CAN2_RX1_interrupt, Startup - .set CAN2_SCE_interrupt, Startup - .set USB_On_The_Go_FS_global_interrupt, Startup + .set Window_Watchdog_interrupt, HaltProc + .set PVD_through_EXTI_Line_detection_interrupt, HaltProc + .set Tamper_interrupt, HaltProc + .set RTC_global_interrupt, HaltProc + .set Flash_global_interrupt, HaltProc + .set RCC_global_interrupt, HaltProc + .set EXTI_Line0_interrupt, HaltProc + .set EXTI_Line1_interrupt, HaltProc + .set EXTI_Line2_interrupt, HaltProc + .set EXTI_Line3_interrupt, HaltProc + .set EXTI_Line4_interrupt, HaltProc + .set DMA1_Channel1_global_interrupt, HaltProc + .set DMA1_Channel2_global_interrupt, HaltProc + .set DMA1_Channel3_global_interrupt, HaltProc + .set DMA1_Channel4_global_interrupt, HaltProc + .set DMA1_Channel5_global_interrupt, HaltProc + .set DMA1_Channel6_global_interrupt, HaltProc + .set DMA1_Channel7_global_interrupt, HaltProc + .set ADC1_and_ADC2_global_interrupt, HaltProc + .set CAN1_TX_interrupts, HaltProc + .set CAN1_RX0_interrupts, HaltProc + .set CAN1_RX1_interrupt, HaltProc + .set CAN1_SCE_interrupt, HaltProc + .set EXTI_Line9_5_interrupts, HaltProc + .set TIM1_Break_interrupt, HaltProc + .set TIM1_Update_interrupt, HaltProc + .set TIM1_Trigger_and_Commutation_interrupts, HaltProc + .set TIM1_Capture_Compare_interrupt, HaltProc + .set TIM2_global_interrupt, HaltProc + .set TIM3_global_interrupt, HaltProc + .set TIM4_global_interrupt, HaltProc + .set I2C1_event_interrupt, HaltProc + .set I2C1_error_interrupt, HaltProc + .set I2C2_event_interrupt, HaltProc + .set I2C2_error_interrupt, HaltProc + .set SPI1_global_interrupt, HaltProc + .set SPI2_global_interrupt, HaltProc + .set USART1_global_interrupt, HaltProc + .set USART2_global_interrupt, HaltProc + .set USART3_global_interrupt, HaltProc + .set EXTI_Line15_10_interrupts, HaltProc + .set RTC_alarm_through_EXTI_line_interrupt, HaltProc + .set USB_OTG_FS_Wakeup_through_EXTI_line_interrupt, HaltProc + .set TIM5_global_interrupt, HaltProc + .set SPI3_global_interrupt, HaltProc + .set UART4_global_interrupt, HaltProc + .set UART5_global_interrupt, HaltProc + .set TIM6_global_interrupt, HaltProc + .set TIM7_global_interrupt, HaltProc + .set DMA2_Channel1_global_interrupt, HaltProc + .set DMA2_Channel2_global_interrupt, HaltProc + .set DMA2_Channel3_global_interrupt, HaltProc + .set DMA2_Channel4_global_interrupt, HaltProc + .set DMA2_Channel5_global_interrupt, HaltProc + .set Ethernet_global_interrupt, HaltProc + .set Ethernet_Wakeup_through_EXTI_line_interrupt, HaltProc + .set CAN2_TX_interrupts, HaltProc + .set CAN2_RX0_interrupts, HaltProc + .set CAN2_RX1_interrupt, HaltProc + .set CAN2_SCE_interrupt, HaltProc + .set USB_On_The_Go_FS_global_interrupt, HaltProc .text end; diff --git a/rtl/embedded/arm/stm32f10x_hd.pp b/rtl/embedded/arm/stm32f10x_hd.pp index 02992654b7..2737ca1c75 100644 --- a/rtl/embedded/arm/stm32f10x_hd.pp +++ b/rtl/embedded/arm/stm32f10x_hd.pp @@ -23,8 +23,6 @@ const APB2Base = PeripheralBase+$10000; AHBBase = PeripheralBase+$20000; - SCS_BASE = $E000E000; - { FSMC } FSMCBank1NOR1 = FSMCBase+$00000000; FSMCBank1NOR2 = FSMCBase+$04000000; @@ -328,51 +326,6 @@ type OBR, WRPR: longword; end; - - TNVICRegisters = record - ISER: array[0..7] of longword; - reserved0: array[0..23] of longword; - ICER: array[0..7] of longword; - reserved1: array[0..23] of longword; - ISPR: array[0..7] of longword; - reserved2: array[0..23] of longword; - ICPR: array[0..7] of longword; - reserved3: array[0..23] of longword; - IABR: array[0..7] of longword; - reserved4: array[0..55] of longword; - IP: array[0..239] of byte; - reserved5: array[0..643] of longword; - STIR: longword; - end; - - TSCBRegisters = record - CPUID, {!< CPU ID Base Register } - ICSR, {!< Interrupt Control State Register } - VTOR, {!< Vector Table Offset Register } - AIRCR, {!< Application Interrupt / Reset Control Register } - SCR, {!< System Control Register } - CCR: longword; {!< Configuration Control Register } - SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } - SHCSR, {!< System Handler Control and State Register } - CFSR, {!< Configurable Fault Status Register } - HFSR, {!< Hard Fault Status Register } - DFSR, {!< Debug Fault Status Register } - MMFAR, {!< Mem Manage Address Register } - BFAR, {!< Bus Fault Address Register } - AFSR: longword; {!< Auxiliary Fault Status Register } - PFR: array[0..1] of longword; {!< Processor Feature Register } - DFR, {!< Debug Feature Register } - ADR: longword; {!< Auxiliary Feature Register } - MMFR: array[0..3] of longword; {!< Memory Model Feature Register } - ISAR: array[0..4] of longword; {!< ISA Feature Register } - end; - - TSysTickRegisters = record - Ctrl, - Load, - Val, - Calib: longword; - end; TFSMC_Bank1 = record BCR1 : longword; @@ -505,15 +458,6 @@ var { CRC } CRC: TCRCRegisters absolute (AHBBase+$3000); - { SCB } - SCB: TSCBRegisters absolute (SCS_BASE+$0D00); - - { SysTick } - SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); - - { NVIC } - NVIC: TNVICRegisters absolute (SCS_BASE+$0100); - { FSMC } FSMC_Bank1 : TFSMC_Bank1 absolute (FSMCBase + $40000000); FSMC_Bank1E : TFSMC_Bank1E absolute (FSMCBase + $40000104); @@ -750,76 +694,76 @@ interrupt_vectors: .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set Window_watchdog_interrupt, Startup - .set PVD_through_EXTI_Line_detection_interrupt, Startup - .set Tamper_interrupt, Startup - .set RTC_global_interrupt, Startup - .set Flash_global_interrupt, Startup - .set RCC_global_interrupt, Startup - .set EXTI_Line0_interrupt, Startup - .set EXTI_Line1_interrupt, Startup - .set EXTI_Line2_interrupt, Startup - .set EXTI_Line3_interrupt, Startup - .set EXTI_Line4_interrupt, Startup - .set DMA1_Channel1_global_interrupt, Startup - .set DMA1_Channel2_global_interrupt, Startup - .set DMA1_Channel3_global_interrupt, Startup - .set DMA1_Channel4_global_interrupt, Startup - .set DMA1_Channel5_global_interrupt, Startup - .set DMA1_Channel6_global_interrupt, Startup - .set DMA1_Channel7_global_interrupt, Startup - .set ADC1_and_ADC2_global_interrupt, Startup - .set USB_High_Priority_or_CAN_TX_interrupts, Startup - .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup - .set CAN_RX1_interrupt, Startup - .set CAN_SCE_interrupt, Startup - .set EXTI_Line9_5_interrupts, Startup - .set TIM1_Break_interrupt, Startup - .set TIM1_Update_interrupt, Startup - .set TIM1_Trigger_and_Commutation_interrupts, Startup - .set TIM1_Capture_Compare_interrupt, Startup - .set TIM2_global_interrupt, Startup - .set TIM3_global_interrupt, Startup - .set TIM4_global_interrupt, Startup - .set I2C1_event_interrupt, Startup - .set I2C1_error_interrupt, Startup - .set I2C2_event_interrupt, Startup - .set I2C2_error_interrupt, Startup - .set SPI1_global_interrupt, Startup - .set SPI2_global_interrupt, Startup - .set USART1_global_interrupt, Startup - .set USART2_global_interrupt, Startup - .set USART3_global_interrupt, Startup - .set EXTI_Line15_10_interrupts, Startup - .set RTC_alarm_through_EXTI_line_interrupt, Startup - .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup - .set TIM8_Break_interrupt, Startup - .set TIM8_Update_interrupt, Startup - .set TIM8_Trigger_and_Commutation_interrupts, Startup - .set TIM8_Capture_Compare_interrupt, Startup - .set ADC3_global_interrupt, Startup - .set FSMC_global_interrupt, Startup - .set SDIO_global_interrupt, Startup - .set TIM5_global_interrupt, Startup - .set SPI3_global_interrupt, Startup - .set UART4_global_interrupt, Startup - .set UART5_global_interrupt, Startup - .set TIM6_global_interrupt, Startup - .set TIM7_global_interrupt, Startup - .set DMA2_Channel1_global_interrupt, Startup - .set DMA2_Channel2_global_interrupt, Startup - .set DMA2_Channel3_global_interrupt, Startup - .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup + .set Window_watchdog_interrupt, HaltProc + .set PVD_through_EXTI_Line_detection_interrupt, HaltProc + .set Tamper_interrupt, HaltProc + .set RTC_global_interrupt, HaltProc + .set Flash_global_interrupt, HaltProc + .set RCC_global_interrupt, HaltProc + .set EXTI_Line0_interrupt, HaltProc + .set EXTI_Line1_interrupt, HaltProc + .set EXTI_Line2_interrupt, HaltProc + .set EXTI_Line3_interrupt, HaltProc + .set EXTI_Line4_interrupt, HaltProc + .set DMA1_Channel1_global_interrupt, HaltProc + .set DMA1_Channel2_global_interrupt, HaltProc + .set DMA1_Channel3_global_interrupt, HaltProc + .set DMA1_Channel4_global_interrupt, HaltProc + .set DMA1_Channel5_global_interrupt, HaltProc + .set DMA1_Channel6_global_interrupt, HaltProc + .set DMA1_Channel7_global_interrupt, HaltProc + .set ADC1_and_ADC2_global_interrupt, HaltProc + .set USB_High_Priority_or_CAN_TX_interrupts, HaltProc + .set USB_Low_Priority_or_CAN_RX0_interrupts, HaltProc + .set CAN_RX1_interrupt, HaltProc + .set CAN_SCE_interrupt, HaltProc + .set EXTI_Line9_5_interrupts, HaltProc + .set TIM1_Break_interrupt, HaltProc + .set TIM1_Update_interrupt, HaltProc + .set TIM1_Trigger_and_Commutation_interrupts, HaltProc + .set TIM1_Capture_Compare_interrupt, HaltProc + .set TIM2_global_interrupt, HaltProc + .set TIM3_global_interrupt, HaltProc + .set TIM4_global_interrupt, HaltProc + .set I2C1_event_interrupt, HaltProc + .set I2C1_error_interrupt, HaltProc + .set I2C2_event_interrupt, HaltProc + .set I2C2_error_interrupt, HaltProc + .set SPI1_global_interrupt, HaltProc + .set SPI2_global_interrupt, HaltProc + .set USART1_global_interrupt, HaltProc + .set USART2_global_interrupt, HaltProc + .set USART3_global_interrupt, HaltProc + .set EXTI_Line15_10_interrupts, HaltProc + .set RTC_alarm_through_EXTI_line_interrupt, HaltProc + .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, HaltProc + .set TIM8_Break_interrupt, HaltProc + .set TIM8_Update_interrupt, HaltProc + .set TIM8_Trigger_and_Commutation_interrupts, HaltProc + .set TIM8_Capture_Compare_interrupt, HaltProc + .set ADC3_global_interrupt, HaltProc + .set FSMC_global_interrupt, HaltProc + .set SDIO_global_interrupt, HaltProc + .set TIM5_global_interrupt, HaltProc + .set SPI3_global_interrupt, HaltProc + .set UART4_global_interrupt, HaltProc + .set UART5_global_interrupt, HaltProc + .set TIM6_global_interrupt, HaltProc + .set TIM7_global_interrupt, HaltProc + .set DMA2_Channel1_global_interrupt, HaltProc + .set DMA2_Channel2_global_interrupt, HaltProc + .set DMA2_Channel3_global_interrupt, HaltProc + .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc .text end; diff --git a/rtl/embedded/arm/stm32f10x_ld.pp b/rtl/embedded/arm/stm32f10x_ld.pp index f8a77a56e6..b358878b9e 100644 --- a/rtl/embedded/arm/stm32f10x_ld.pp +++ b/rtl/embedded/arm/stm32f10x_ld.pp @@ -23,8 +23,6 @@ const APB2Base = PeripheralBase+$10000; AHBBase = PeripheralBase+$20000; - SCS_BASE = $E000E000; - { FSMC } FSMCBank1NOR1 = FSMCBase+$00000000; FSMCBank1NOR2 = FSMCBase+$04000000; @@ -329,51 +327,6 @@ type WRPR: longword; end; - TNVICRegisters = record - ISER: array[0..7] of longword; - reserved0: array[0..23] of longword; - ICER: array[0..7] of longword; - reserved1: array[0..23] of longword; - ISPR: array[0..7] of longword; - reserved2: array[0..23] of longword; - ICPR: array[0..7] of longword; - reserved3: array[0..23] of longword; - IABR: array[0..7] of longword; - reserved4: array[0..55] of longword; - IP: array[0..239] of byte; - reserved5: array[0..643] of longword; - STIR: longword; - end; - - TSCBRegisters = record - CPUID, {!< CPU ID Base Register } - ICSR, {!< Interrupt Control State Register } - VTOR, {!< Vector Table Offset Register } - AIRCR, {!< Application Interrupt / Reset Control Register } - SCR, {!< System Control Register } - CCR: longword; {!< Configuration Control Register } - SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } - SHCSR, {!< System Handler Control and State Register } - CFSR, {!< Configurable Fault Status Register } - HFSR, {!< Hard Fault Status Register } - DFSR, {!< Debug Fault Status Register } - MMFAR, {!< Mem Manage Address Register } - BFAR, {!< Bus Fault Address Register } - AFSR: longword; {!< Auxiliary Fault Status Register } - PFR: array[0..1] of longword; {!< Processor Feature Register } - DFR, {!< Debug Feature Register } - ADR: longword; {!< Auxiliary Feature Register } - MMFR: array[0..3] of longword; {!< Memory Model Feature Register } - ISAR: array[0..4] of longword; {!< ISA Feature Register } - end; - - TSysTickRegisters = record - Ctrl, - Load, - Val, - Calib: longword; - end; - {$ALIGN 2} var { Timers } @@ -458,15 +411,6 @@ var { CRC } CRC: TCRCRegisters absolute (AHBBase+$3000); - { SCB } - SCB: TSCBRegisters absolute (SCS_BASE+$0D00); - - { SysTick } - SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); - - { NVIC } - NVIC: TNVICRegisters absolute (SCS_BASE+$0100); - implementation procedure NMI_interrupt; external name 'NMI_interrupt'; @@ -696,76 +640,76 @@ interrupt_vectors: .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set Window_watchdog_interrupt, Startup - .set PVD_through_EXTI_Line_detection_interrupt, Startup - .set Tamper_interrupt, Startup - .set RTC_global_interrupt, Startup - .set Flash_global_interrupt, Startup - .set RCC_global_interrupt, Startup - .set EXTI_Line0_interrupt, Startup - .set EXTI_Line1_interrupt, Startup - .set EXTI_Line2_interrupt, Startup - .set EXTI_Line3_interrupt, Startup - .set EXTI_Line4_interrupt, Startup - .set DMA1_Channel1_global_interrupt, Startup - .set DMA1_Channel2_global_interrupt, Startup - .set DMA1_Channel3_global_interrupt, Startup - .set DMA1_Channel4_global_interrupt, Startup - .set DMA1_Channel5_global_interrupt, Startup - .set DMA1_Channel6_global_interrupt, Startup - .set DMA1_Channel7_global_interrupt, Startup - .set ADC1_and_ADC2_global_interrupt, Startup - .set USB_High_Priority_or_CAN_TX_interrupts, Startup - .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup - .set CAN_RX1_interrupt, Startup - .set CAN_SCE_interrupt, Startup - .set EXTI_Line9_5_interrupts, Startup - .set TIM1_Break_interrupt, Startup - .set TIM1_Update_interrupt, Startup - .set TIM1_Trigger_and_Commutation_interrupts, Startup - .set TIM1_Capture_Compare_interrupt, Startup - .set TIM2_global_interrupt, Startup - .set TIM3_global_interrupt, Startup - .set TIM4_global_interrupt, Startup - .set I2C1_event_interrupt, Startup - .set I2C1_error_interrupt, Startup - .set I2C2_event_interrupt, Startup - .set I2C2_error_interrupt, Startup - .set SPI1_global_interrupt, Startup - .set SPI2_global_interrupt, Startup - .set USART1_global_interrupt, Startup - .set USART2_global_interrupt, Startup - .set USART3_global_interrupt, Startup - .set EXTI_Line15_10_interrupts, Startup - .set RTC_alarm_through_EXTI_line_interrupt, Startup - .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup - .set TIM8_Break_interrupt, Startup - .set TIM8_Update_interrupt, Startup - .set TIM8_Trigger_and_Commutation_interrupts, Startup - .set TIM8_Capture_Compare_interrupt, Startup - .set ADC3_global_interrupt, Startup - .set FSMC_global_interrupt, Startup - .set SDIO_global_interrupt, Startup - .set TIM5_global_interrupt, Startup - .set SPI3_global_interrupt, Startup - .set UART4_global_interrupt, Startup - .set UART5_global_interrupt, Startup - .set TIM6_global_interrupt, Startup - .set TIM7_global_interrupt, Startup - .set DMA2_Channel1_global_interrupt, Startup - .set DMA2_Channel2_global_interrupt, Startup - .set DMA2_Channel3_global_interrupt, Startup - .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup + .set Window_watchdog_interrupt, HaltProc + .set PVD_through_EXTI_Line_detection_interrupt, HaltProc + .set Tamper_interrupt, HaltProc + .set RTC_global_interrupt, HaltProc + .set Flash_global_interrupt, HaltProc + .set RCC_global_interrupt, HaltProc + .set EXTI_Line0_interrupt, HaltProc + .set EXTI_Line1_interrupt, HaltProc + .set EXTI_Line2_interrupt, HaltProc + .set EXTI_Line3_interrupt, HaltProc + .set EXTI_Line4_interrupt, HaltProc + .set DMA1_Channel1_global_interrupt, HaltProc + .set DMA1_Channel2_global_interrupt, HaltProc + .set DMA1_Channel3_global_interrupt, HaltProc + .set DMA1_Channel4_global_interrupt, HaltProc + .set DMA1_Channel5_global_interrupt, HaltProc + .set DMA1_Channel6_global_interrupt, HaltProc + .set DMA1_Channel7_global_interrupt, HaltProc + .set ADC1_and_ADC2_global_interrupt, HaltProc + .set USB_High_Priority_or_CAN_TX_interrupts, HaltProc + .set USB_Low_Priority_or_CAN_RX0_interrupts, HaltProc + .set CAN_RX1_interrupt, HaltProc + .set CAN_SCE_interrupt, HaltProc + .set EXTI_Line9_5_interrupts, HaltProc + .set TIM1_Break_interrupt, HaltProc + .set TIM1_Update_interrupt, HaltProc + .set TIM1_Trigger_and_Commutation_interrupts, HaltProc + .set TIM1_Capture_Compare_interrupt, HaltProc + .set TIM2_global_interrupt, HaltProc + .set TIM3_global_interrupt, HaltProc + .set TIM4_global_interrupt, HaltProc + .set I2C1_event_interrupt, HaltProc + .set I2C1_error_interrupt, HaltProc + .set I2C2_event_interrupt, HaltProc + .set I2C2_error_interrupt, HaltProc + .set SPI1_global_interrupt, HaltProc + .set SPI2_global_interrupt, HaltProc + .set USART1_global_interrupt, HaltProc + .set USART2_global_interrupt, HaltProc + .set USART3_global_interrupt, HaltProc + .set EXTI_Line15_10_interrupts, HaltProc + .set RTC_alarm_through_EXTI_line_interrupt, HaltProc + .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, HaltProc + .set TIM8_Break_interrupt, HaltProc + .set TIM8_Update_interrupt, HaltProc + .set TIM8_Trigger_and_Commutation_interrupts, HaltProc + .set TIM8_Capture_Compare_interrupt, HaltProc + .set ADC3_global_interrupt, HaltProc + .set FSMC_global_interrupt, HaltProc + .set SDIO_global_interrupt, HaltProc + .set TIM5_global_interrupt, HaltProc + .set SPI3_global_interrupt, HaltProc + .set UART4_global_interrupt, HaltProc + .set UART5_global_interrupt, HaltProc + .set TIM6_global_interrupt, HaltProc + .set TIM7_global_interrupt, HaltProc + .set DMA2_Channel1_global_interrupt, HaltProc + .set DMA2_Channel2_global_interrupt, HaltProc + .set DMA2_Channel3_global_interrupt, HaltProc + .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc .text end; diff --git a/rtl/embedded/arm/stm32f10x_md.pp b/rtl/embedded/arm/stm32f10x_md.pp index a43a4a92b9..2242007e91 100644 --- a/rtl/embedded/arm/stm32f10x_md.pp +++ b/rtl/embedded/arm/stm32f10x_md.pp @@ -23,8 +23,6 @@ const APB2Base = PeripheralBase+$10000; AHBBase = PeripheralBase+$20000; - SCS_BASE = $E000E000; - { FSMC } FSMCBank1NOR1 = FSMCBase+$00000000; FSMCBank1NOR2 = FSMCBase+$04000000; @@ -329,51 +327,6 @@ type WRPR: longword; end; - TNVICRegisters = record - ISER: array[0..7] of longword; - reserved0: array[0..23] of longword; - ICER: array[0..7] of longword; - reserved1: array[0..23] of longword; - ISPR: array[0..7] of longword; - reserved2: array[0..23] of longword; - ICPR: array[0..7] of longword; - reserved3: array[0..23] of longword; - IABR: array[0..7] of longword; - reserved4: array[0..55] of longword; - IP: array[0..239] of byte; - reserved5: array[0..643] of longword; - STIR: longword; - end; - - TSCBRegisters = record - CPUID, {!< CPU ID Base Register } - ICSR, {!< Interrupt Control State Register } - VTOR, {!< Vector Table Offset Register } - AIRCR, {!< Application Interrupt / Reset Control Register } - SCR, {!< System Control Register } - CCR: longword; {!< Configuration Control Register } - SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } - SHCSR, {!< System Handler Control and State Register } - CFSR, {!< Configurable Fault Status Register } - HFSR, {!< Hard Fault Status Register } - DFSR, {!< Debug Fault Status Register } - MMFAR, {!< Mem Manage Address Register } - BFAR, {!< Bus Fault Address Register } - AFSR: longword; {!< Auxiliary Fault Status Register } - PFR: array[0..1] of longword; {!< Processor Feature Register } - DFR, {!< Debug Feature Register } - ADR: longword; {!< Auxiliary Feature Register } - MMFR: array[0..3] of longword; {!< Memory Model Feature Register } - ISAR: array[0..4] of longword; {!< ISA Feature Register } - end; - - TSysTickRegisters = record - Ctrl, - Load, - Val, - Calib: longword; - end; - {$ALIGN 2} var { Timers } @@ -458,15 +411,6 @@ var { CRC } CRC: TCRCRegisters absolute (AHBBase+$3000); - { SCB } - SCB: TSCBRegisters absolute (SCS_BASE+$0D00); - - { SysTick } - SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); - - { NVIC } - NVIC: TNVICRegisters absolute (SCS_BASE+$0100); - implementation procedure NMI_interrupt; external name 'NMI_interrupt'; @@ -696,76 +640,76 @@ interrupt_vectors: .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set Window_watchdog_interrupt, Startup - .set PVD_through_EXTI_Line_detection_interrupt, Startup - .set Tamper_interrupt, Startup - .set RTC_global_interrupt, Startup - .set Flash_global_interrupt, Startup - .set RCC_global_interrupt, Startup - .set EXTI_Line0_interrupt, Startup - .set EXTI_Line1_interrupt, Startup - .set EXTI_Line2_interrupt, Startup - .set EXTI_Line3_interrupt, Startup - .set EXTI_Line4_interrupt, Startup - .set DMA1_Channel1_global_interrupt, Startup - .set DMA1_Channel2_global_interrupt, Startup - .set DMA1_Channel3_global_interrupt, Startup - .set DMA1_Channel4_global_interrupt, Startup - .set DMA1_Channel5_global_interrupt, Startup - .set DMA1_Channel6_global_interrupt, Startup - .set DMA1_Channel7_global_interrupt, Startup - .set ADC1_and_ADC2_global_interrupt, Startup - .set USB_High_Priority_or_CAN_TX_interrupts, Startup - .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup - .set CAN_RX1_interrupt, Startup - .set CAN_SCE_interrupt, Startup - .set EXTI_Line9_5_interrupts, Startup - .set TIM1_Break_interrupt, Startup - .set TIM1_Update_interrupt, Startup - .set TIM1_Trigger_and_Commutation_interrupts, Startup - .set TIM1_Capture_Compare_interrupt, Startup - .set TIM2_global_interrupt, Startup - .set TIM3_global_interrupt, Startup - .set TIM4_global_interrupt, Startup - .set I2C1_event_interrupt, Startup - .set I2C1_error_interrupt, Startup - .set I2C2_event_interrupt, Startup - .set I2C2_error_interrupt, Startup - .set SPI1_global_interrupt, Startup - .set SPI2_global_interrupt, Startup - .set USART1_global_interrupt, Startup - .set USART2_global_interrupt, Startup - .set USART3_global_interrupt, Startup - .set EXTI_Line15_10_interrupts, Startup - .set RTC_alarm_through_EXTI_line_interrupt, Startup - .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup - .set TIM8_Break_interrupt, Startup - .set TIM8_Update_interrupt, Startup - .set TIM8_Trigger_and_Commutation_interrupts, Startup - .set TIM8_Capture_Compare_interrupt, Startup - .set ADC3_global_interrupt, Startup - .set FSMC_global_interrupt, Startup - .set SDIO_global_interrupt, Startup - .set TIM5_global_interrupt, Startup - .set SPI3_global_interrupt, Startup - .set UART4_global_interrupt, Startup - .set UART5_global_interrupt, Startup - .set TIM6_global_interrupt, Startup - .set TIM7_global_interrupt, Startup - .set DMA2_Channel1_global_interrupt, Startup - .set DMA2_Channel2_global_interrupt, Startup - .set DMA2_Channel3_global_interrupt, Startup - .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup + .set Window_watchdog_interrupt, HaltProc + .set PVD_through_EXTI_Line_detection_interrupt, HaltProc + .set Tamper_interrupt, HaltProc + .set RTC_global_interrupt, HaltProc + .set Flash_global_interrupt, HaltProc + .set RCC_global_interrupt, HaltProc + .set EXTI_Line0_interrupt, HaltProc + .set EXTI_Line1_interrupt, HaltProc + .set EXTI_Line2_interrupt, HaltProc + .set EXTI_Line3_interrupt, HaltProc + .set EXTI_Line4_interrupt, HaltProc + .set DMA1_Channel1_global_interrupt, HaltProc + .set DMA1_Channel2_global_interrupt, HaltProc + .set DMA1_Channel3_global_interrupt, HaltProc + .set DMA1_Channel4_global_interrupt, HaltProc + .set DMA1_Channel5_global_interrupt, HaltProc + .set DMA1_Channel6_global_interrupt, HaltProc + .set DMA1_Channel7_global_interrupt, HaltProc + .set ADC1_and_ADC2_global_interrupt, HaltProc + .set USB_High_Priority_or_CAN_TX_interrupts, HaltProc + .set USB_Low_Priority_or_CAN_RX0_interrupts, HaltProc + .set CAN_RX1_interrupt, HaltProc + .set CAN_SCE_interrupt, HaltProc + .set EXTI_Line9_5_interrupts, HaltProc + .set TIM1_Break_interrupt, HaltProc + .set TIM1_Update_interrupt, HaltProc + .set TIM1_Trigger_and_Commutation_interrupts, HaltProc + .set TIM1_Capture_Compare_interrupt, HaltProc + .set TIM2_global_interrupt, HaltProc + .set TIM3_global_interrupt, HaltProc + .set TIM4_global_interrupt, HaltProc + .set I2C1_event_interrupt, HaltProc + .set I2C1_error_interrupt, HaltProc + .set I2C2_event_interrupt, HaltProc + .set I2C2_error_interrupt, HaltProc + .set SPI1_global_interrupt, HaltProc + .set SPI2_global_interrupt, HaltProc + .set USART1_global_interrupt, HaltProc + .set USART2_global_interrupt, HaltProc + .set USART3_global_interrupt, HaltProc + .set EXTI_Line15_10_interrupts, HaltProc + .set RTC_alarm_through_EXTI_line_interrupt, HaltProc + .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, HaltProc + .set TIM8_Break_interrupt, HaltProc + .set TIM8_Update_interrupt, HaltProc + .set TIM8_Trigger_and_Commutation_interrupts, HaltProc + .set TIM8_Capture_Compare_interrupt, HaltProc + .set ADC3_global_interrupt, HaltProc + .set FSMC_global_interrupt, HaltProc + .set SDIO_global_interrupt, HaltProc + .set TIM5_global_interrupt, HaltProc + .set SPI3_global_interrupt, HaltProc + .set UART4_global_interrupt, HaltProc + .set UART5_global_interrupt, HaltProc + .set TIM6_global_interrupt, HaltProc + .set TIM7_global_interrupt, HaltProc + .set DMA2_Channel1_global_interrupt, HaltProc + .set DMA2_Channel2_global_interrupt, HaltProc + .set DMA2_Channel3_global_interrupt, HaltProc + .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc .text end; diff --git a/rtl/embedded/arm/stm32f10x_xl.pp b/rtl/embedded/arm/stm32f10x_xl.pp index d61f57071f..eaf05a5f31 100644 --- a/rtl/embedded/arm/stm32f10x_xl.pp +++ b/rtl/embedded/arm/stm32f10x_xl.pp @@ -23,8 +23,6 @@ const APB2Base = PeripheralBase+$10000; AHBBase = PeripheralBase+$20000; - SCS_BASE = $E000E000; - { FSMC } FSMCBank1NOR1 = FSMCBase+$00000000; FSMCBank1NOR2 = FSMCBase+$04000000; @@ -328,51 +326,6 @@ type OBR, WRPR: longword; end; - - TNVICRegisters = record - ISER: array[0..7] of longword; - reserved0: array[0..23] of longword; - ICER: array[0..7] of longword; - reserved1: array[0..23] of longword; - ISPR: array[0..7] of longword; - reserved2: array[0..23] of longword; - ICPR: array[0..7] of longword; - reserved3: array[0..23] of longword; - IABR: array[0..7] of longword; - reserved4: array[0..55] of longword; - IP: array[0..239] of byte; - reserved5: array[0..643] of longword; - STIR: longword; - end; - - TSCBRegisters = record - CPUID, {!< CPU ID Base Register } - ICSR, {!< Interrupt Control State Register } - VTOR, {!< Vector Table Offset Register } - AIRCR, {!< Application Interrupt / Reset Control Register } - SCR, {!< System Control Register } - CCR: longword; {!< Configuration Control Register } - SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } - SHCSR, {!< System Handler Control and State Register } - CFSR, {!< Configurable Fault Status Register } - HFSR, {!< Hard Fault Status Register } - DFSR, {!< Debug Fault Status Register } - MMFAR, {!< Mem Manage Address Register } - BFAR, {!< Bus Fault Address Register } - AFSR: longword; {!< Auxiliary Fault Status Register } - PFR: array[0..1] of longword; {!< Processor Feature Register } - DFR, {!< Debug Feature Register } - ADR: longword; {!< Auxiliary Feature Register } - MMFR: array[0..3] of longword; {!< Memory Model Feature Register } - ISAR: array[0..4] of longword; {!< ISA Feature Register } - end; - - TSysTickRegisters = record - Ctrl, - Load, - Val, - Calib: longword; - end; TFSMC_Bank1 = record BCR1 : longword; @@ -505,15 +458,6 @@ var { CRC } CRC: TCRCRegisters absolute (AHBBase+$3000); - { SCB } - SCB: TSCBRegisters absolute (SCS_BASE+$0D00); - - { SysTick } - SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); - - { NVIC } - NVIC: TNVICRegisters absolute (SCS_BASE+$0100); - { FSMC } FSMC_Bank1 : TFSMC_Bank1 absolute (FSMCBase + $40000000); FSMC_Bank1E : TFSMC_Bank1E absolute (FSMCBase + $40000104); @@ -751,76 +695,76 @@ interrupt_vectors: .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts - .set NMI_interrupt, Startup - .set Hardfault_interrupt, Startup - .set MemManage_interrupt, Startup - .set BusFault_interrupt, Startup - .set UsageFault_interrupt, Startup - .set SWI_interrupt, Startup - .set DebugMonitor_interrupt, Startup - .set PendingSV_interrupt, Startup - .set SysTick_interrupt, Startup + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc - .set Window_watchdog_interrupt, Startup - .set PVD_through_EXTI_Line_detection_interrupt, Startup - .set Tamper_interrupt, Startup - .set RTC_global_interrupt, Startup - .set Flash_global_interrupt, Startup - .set RCC_global_interrupt, Startup - .set EXTI_Line0_interrupt, Startup - .set EXTI_Line1_interrupt, Startup - .set EXTI_Line2_interrupt, Startup - .set EXTI_Line3_interrupt, Startup - .set EXTI_Line4_interrupt, Startup - .set DMA1_Channel1_global_interrupt, Startup - .set DMA1_Channel2_global_interrupt, Startup - .set DMA1_Channel3_global_interrupt, Startup - .set DMA1_Channel4_global_interrupt, Startup - .set DMA1_Channel5_global_interrupt, Startup - .set DMA1_Channel6_global_interrupt, Startup - .set DMA1_Channel7_global_interrupt, Startup - .set ADC1_and_ADC2_global_interrupt, Startup - .set USB_High_Priority_or_CAN_TX_interrupts, Startup - .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup - .set CAN_RX1_interrupt, Startup - .set CAN_SCE_interrupt, Startup - .set EXTI_Line9_5_interrupts, Startup - .set TIM1_Break_TIM9_global_interrupt, Startup - .set TIM1_Update_TIM10_global_interrupt, Startup - .set TIM1_Trigger_and_Commutation_TIM11_global_interrupts, Startup - .set TIM1_Capture_Compare_interrupt, Startup - .set TIM2_global_interrupt, Startup - .set TIM3_global_interrupt, Startup - .set TIM4_global_interrupt, Startup - .set I2C1_event_interrupt, Startup - .set I2C1_error_interrupt, Startup - .set I2C2_event_interrupt, Startup - .set I2C2_error_interrupt, Startup - .set SPI1_global_interrupt, Startup - .set SPI2_global_interrupt, Startup - .set USART1_global_interrupt, Startup - .set USART2_global_interrupt, Startup - .set USART3_global_interrupt, Startup - .set EXTI_Line15_10_interrupts, Startup - .set RTC_alarm_through_EXTI_line_interrupt, Startup - .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup - .set TIM8_Break_TIM12_global_interrupt, Startup - .set TIM8_Update_TIM13_global_interrupt, Startup - .set TIM8_Trigger_and_Commutation_TIM14_global_interrupts, Startup - .set TIM8_Capture_Compare_interrupt, Startup - .set ADC3_global_interrupt, Startup - .set FSMC_global_interrupt, Startup - .set SDIO_global_interrupt, Startup - .set TIM5_global_interrupt, Startup - .set SPI3_global_interrupt, Startup - .set UART4_global_interrupt, Startup - .set UART5_global_interrupt, Startup - .set TIM6_global_interrupt, Startup - .set TIM7_global_interrupt, Startup - .set DMA2_Channel1_global_interrupt, Startup - .set DMA2_Channel2_global_interrupt, Startup - .set DMA2_Channel3_global_interrupt, Startup - .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup + .set Window_watchdog_interrupt, HaltProc + .set PVD_through_EXTI_Line_detection_interrupt, HaltProc + .set Tamper_interrupt, HaltProc + .set RTC_global_interrupt, HaltProc + .set Flash_global_interrupt, HaltProc + .set RCC_global_interrupt, HaltProc + .set EXTI_Line0_interrupt, HaltProc + .set EXTI_Line1_interrupt, HaltProc + .set EXTI_Line2_interrupt, HaltProc + .set EXTI_Line3_interrupt, HaltProc + .set EXTI_Line4_interrupt, HaltProc + .set DMA1_Channel1_global_interrupt, HaltProc + .set DMA1_Channel2_global_interrupt, HaltProc + .set DMA1_Channel3_global_interrupt, HaltProc + .set DMA1_Channel4_global_interrupt, HaltProc + .set DMA1_Channel5_global_interrupt, HaltProc + .set DMA1_Channel6_global_interrupt, HaltProc + .set DMA1_Channel7_global_interrupt, HaltProc + .set ADC1_and_ADC2_global_interrupt, HaltProc + .set USB_High_Priority_or_CAN_TX_interrupts, HaltProc + .set USB_Low_Priority_or_CAN_RX0_interrupts, HaltProc + .set CAN_RX1_interrupt, HaltProc + .set CAN_SCE_interrupt, HaltProc + .set EXTI_Line9_5_interrupts, HaltProc + .set TIM1_Break_TIM9_global_interrupt, HaltProc + .set TIM1_Update_TIM10_global_interrupt, HaltProc + .set TIM1_Trigger_and_Commutation_TIM11_global_interrupts, HaltProc + .set TIM1_Capture_Compare_interrupt, HaltProc + .set TIM2_global_interrupt, HaltProc + .set TIM3_global_interrupt, HaltProc + .set TIM4_global_interrupt, HaltProc + .set I2C1_event_interrupt, HaltProc + .set I2C1_error_interrupt, HaltProc + .set I2C2_event_interrupt, HaltProc + .set I2C2_error_interrupt, HaltProc + .set SPI1_global_interrupt, HaltProc + .set SPI2_global_interrupt, HaltProc + .set USART1_global_interrupt, HaltProc + .set USART2_global_interrupt, HaltProc + .set USART3_global_interrupt, HaltProc + .set EXTI_Line15_10_interrupts, HaltProc + .set RTC_alarm_through_EXTI_line_interrupt, HaltProc + .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, HaltProc + .set TIM8_Break_TIM12_global_interrupt, HaltProc + .set TIM8_Update_TIM13_global_interrupt, HaltProc + .set TIM8_Trigger_and_Commutation_TIM14_global_interrupts, HaltProc + .set TIM8_Capture_Compare_interrupt, HaltProc + .set ADC3_global_interrupt, HaltProc + .set FSMC_global_interrupt, HaltProc + .set SDIO_global_interrupt, HaltProc + .set TIM5_global_interrupt, HaltProc + .set SPI3_global_interrupt, HaltProc + .set UART4_global_interrupt, HaltProc + .set UART5_global_interrupt, HaltProc + .set TIM6_global_interrupt, HaltProc + .set TIM7_global_interrupt, HaltProc + .set DMA2_Channel1_global_interrupt, HaltProc + .set DMA2_Channel2_global_interrupt, HaltProc + .set DMA2_Channel3_global_interrupt, HaltProc + .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc .text end; diff --git a/rtl/embedded/arm/xmc4500.pp b/rtl/embedded/arm/xmc4500.pp new file mode 100644 index 0000000000..cbadde17f0 --- /dev/null +++ b/rtl/embedded/arm/xmc4500.pp @@ -0,0 +1,837 @@ +{ +Register definitions and utility code for XMC450x series + +Created by Jeppe Johansen 2012 - jeppe@j-software.dk +} +unit xmc4500; + +{$goto on} + +interface + +type + TBitvector32 = bitpacked array[0..31] of 0..1; + +{$PACKRECORDS 2} +const + Peripheral0Base = $40000000; + Peripheral1Base = $48000000; + Peripheral2Base = $50000000; + Peripheral3Base = $58000000; + + SCUBase = Peripheral2Base+$4000; + + GCUBase = SCUBase+$0000; + PCUBase = SCUBase+$0200; + HCUBase = SCUBase+$0300; + RCUBase = SCUBase+$0400; + CCUBase = SCUBase+$0600; + +type + TPBARegisters = record + STS, + WADDR: longword; + end; + + TFLASHRegisters = record + res1: array[0..1] of longword; + ID: longword; + res2: longword; + FSR, + FCON, + MARP, + PROCON0, + PROCON1, + PROCON2: longword; + end; + + TWDTRegisters = record + ID, + CTR, + SRV, + TIM, + WLB, + WUB, + WDTSTS, + WDTCLR: longword; + end; + + TRTCRegisters = record + ID, + CTR, + RAWSTAT, + STSSR, + MSKSR, + CLRSR, + ATIM0, + ATIM1, + TIM0, + TIM1: longword; + end; + + TLEDTSRegisters = record + ID, + GLOBCTL, + FNCTL, + EVFR, + TSVAL, + LINE0, + LINE1, + LDCMP0, + LDCMP1, + TSCMP0, + TSCMP1: longword; + end; + + TEBURegisters = record + CLC, + MODCON, + ID, + USERCON, + res0,res1, + ADDRSEL0, + ADDRSEL1, + ADDRSEL2, + ADDRSEL3, + BUSRCON0, + BUSRAP0, + BUSWCON0, + BUSWAP0, + BUSRCON1, + BUSRAP1, + BUSWCON1, + BUSWAP1, + BUSRCON2, + BUSRAP2, + BUSWCON2, + BUSWAP2, + BUSRCON3, + BUSRAP3, + BUSWCON3, + BUSWAP3, + SDRMCON, + SDRMOD, + SDRMREF, + SDRSTAT: longword; + end; + + TETHRegisters = record + MacConfiguration, + MacFrameFilter, + HashTableHigh, + HashTableLow, + GmiiAddress, + GmiiData, + FlowControl, + VlanTag, + Version, + Debug, + RemoteWakeUpFrameFilter, + PmtControlStatus, + res0,res1, + InterruptStatus, + InterruptMask, + MacAddress0High, + MacAddress0Low, + MacAddress1High, + MacAddress1Low, + MacAddress2High, + MacAddress2Low, + MacAddress3High, + MacAddress3Low: longword; + res2: array[0..38] of longword; + // $100 - $288 MMC Management Counters + MmcRegs: array[0..96] of longword; + res3: array[0..286] of longword; + // $700 - $72C IEEE1588 + TimestampControl, + SubSecondIncrement, + SystemTimeSeconds, + SystemTimeNanoseconds, + SystemTimeSecondsUpdate, + SystemTimeNanosecondsUpdate, + TimestampAddend, + TargetTimeSeconds, + TargetTimeNanoseconds, + SystemTimeHigherWordSeconds, + TimestampStatus, + PpsControl: longword; + res4: array[0..563] of longword; + // $1000 - $1024 DMA + BusMode, + TransmitPollDemand, + ReceivePollDemand, + ReceiveDescriptorListAddress, + TransmitDescriptorListAddress, + Status, + OperationMode, + InterruptEnable, + MissedFrameAndBufferOverflowCounter, + ReceiveInterruptWatchdogTimer, + res5, + AhbStatus: longword; + doNotUse: array[0..5] of longword; + CurrentHostTransmitDescriptor, + CurrentHostReceiveDescriptor, + CurrentHostTransmitBufferAddress, + CurrentHostReceiveBufferAddress, + HWFeatures: longword; + end; + + TGPIORegisters = record + Output, + OMR, + res0,res1: longword; + + IOCR: array[0..3] of longword; + + res2, + Input: longword; + res3: array[0..5] of longword; + + PDR: array[0..1] of longword; + res5: array[0..5] of longword; + + PDISC: longword; + res6: array[0..2] of longword; + + PPS, + HWSel: longword; + res7: array[0..33] of longword; + end; + +{$ALIGN 2} +var + // Peripheral bus registers + PBA0: TPBARegisters absolute Peripheral0Base; + PBA1: TPBARegisters absolute Peripheral1Base; + + // PMU - Program memory unit + PMU0_ID: longword absolute Peripheral3Base+$0508; + + // PREF - Prefetch unit + PREF_PCON: longword absolute Peripheral3Base+$04000; + + FLASH0: TFLASHRegisters absolute Peripheral3Base+$02000; + + WDT: TWDTRegisters absolute Peripheral2Base+$08000; + + RTC: TRTCRegisters absolute Peripheral2Base+$04A00; + + LEDTS0: TLEDTSRegisters absolute Peripheral1Base+$10000; + + EBU: TEBURegisters absolute Peripheral3Base+$08000; + + ETH: TETHRegisters absolute Peripheral2Base+$0C000; + + // GPIO + P0: TGPIORegisters absolute Peripheral1Base+$28000; + P1: TGPIORegisters absolute Peripheral1Base+$28100; + P2: TGPIORegisters absolute Peripheral1Base+$28200; + P3: TGPIORegisters absolute Peripheral1Base+$28300; + P4: TGPIORegisters absolute Peripheral1Base+$28400; + P5: TGPIORegisters absolute Peripheral1Base+$28500; + P6: TGPIORegisters absolute Peripheral1Base+$28600; + P14: TGPIORegisters absolute Peripheral1Base+$28E00; + P15: TGPIORegisters absolute Peripheral1Base+$28F00; + + SDMMC_BLOCK_SIZE: longword absolute Peripheral1Base+$1C004; + SDMMC_BLOCK_COUNT: longword absolute Peripheral1Base+$1C006; + SDMMC_ARGUMENT1: longword absolute Peripheral1Base+$1C008; + SDMMC_TRANSFER_MODE: longword absolute Peripheral1Base+$1C00C; + SDMMC_COMMAND: longword absolute Peripheral1Base+$1C00E; + SDMMC_RESPONSE0: longword absolute Peripheral1Base+$1C010; + SDMMC_RESPONSE2: longword absolute Peripheral1Base+$1C014; + SDMMC_RESPONSE4: longword absolute Peripheral1Base+$1C018; + SDMMC_RESPONSE6: longword absolute Peripheral1Base+$1C01C; + SDMMC_DATA_BUFFER: longword absolute Peripheral1Base+$1C020; + SDMMC_PRESENT_STATE: longword absolute Peripheral1Base+$1C024; + SDMMC_HOST_CTRL: longword absolute Peripheral1Base+$1C028; + SDMMC_POWER_CTRL: longword absolute Peripheral1Base+$1C029; + SDMMC_BLOCK_GAP_CTRL: longword absolute Peripheral1Base+$1C02A; + SDMMC_WAKEUP_CTRL: longword absolute Peripheral1Base+$1C02B; + SDMMC_CLOCK_CTRL: longword absolute Peripheral1Base+$1C02C; + SDMMC_TIMEOUT_CTRL: longword absolute Peripheral1Base+$1C02E; + SDMMC_SW_RESET: longword absolute Peripheral1Base+$1C02F; + SDMMC_INT_STATUS_NORM: longword absolute Peripheral1Base+$1C030; + SDMMC_INT_STATUS_ERR: longword absolute Peripheral1Base+$1C032; + SDMMC_EN_INT_STATUS_NORM: longword absolute Peripheral1Base+$1C034; + SDMMC_EN_INT_STATUS_ERR: longword absolute Peripheral1Base+$1C036; + SDMMC_EN_INT_SIGNAL_NORM: longword absolute Peripheral1Base+$1C038; + SDMMC_ACMD_ERR_STATUS: longword absolute Peripheral1Base+$1C03C; + SDMMC_FORCE_EVENT_ACMD_ERR_STATUS: longword absolute Peripheral1Base+$1C050; + SDMMC_FORCE_EVENT_ERR_STATUS: longword absolute Peripheral1Base+$1C052; + SDMMC_DEBUG_SEL: longword absolute Peripheral1Base+$1C074; + SDMMC_SPI: longword absolute Peripheral1Base+$1C0F0; + SDMMC_SLOT_INT_STATUS: longword absolute Peripheral1Base+$1C0FC; + + GCU_ID: longword absolute GCUBase+$000; + GCU_IDCHIP: longword absolute GCUBase+$004; + GCU_IDMANUF: longword absolute GCUBase+$008; + GCU_STCON: longword absolute GCUBase+$010; + GCU_GPR0: longword absolute GCUBase+$02C; + GCU_GPR1: longword absolute GCUBase+$030; + GCU_ETH0_CON: longword absolute GCUBase+$040; + GCU_CCUCON: longword absolute GCUBase+$04C; + GCU_SRSTAT: longword absolute GCUBase+$074; + GCU_SRRAW: longword absolute GCUBase+$078; + GCU_SRMSK: longword absolute GCUBase+$07C; + GCU_SRCLR: longword absolute GCUBase+$080; + GCU_SRSET: longword absolute GCUBase+$084; + GCU_NMIREQEN: longword absolute GCUBase+$088; + GCU_DTSCON: longword absolute GCUBase+$08C; + GCU_DTSSTAT: longword absolute GCUBase+$090; + GCU_SDMMCDEL: longword absolute GCUBase+$09C; + GCU_G0RCEN: longword absolute GCUBase+$0A0; + GCU_G1RCEN: longword absolute GCUBase+$0A4; + GCU_MIRRSTS: longword absolute GCUBase+$0C4; + GCU_RMACR: longword absolute GCUBase+$0C8; + GCU_RMADATA: longword absolute GCUBase+$0CC; + GCU_PEEN: longword absolute GCUBase+$13C; + GCU_MCHKCON: longword absolute GCUBase+$140; + GCU_PETE: longword absolute GCUBase+$144; + GCU_PERSTEN: longword absolute GCUBase+$147; + GCU_PEFLAG: longword absolute GCUBase+$150; + GCU_PMTPR: longword absolute GCUBase+$154; + GCU_PMTSR: longword absolute GCUBase+$158; + GCU_TRAPSTAT: longword absolute GCUBase+$160; + GCU_TRAPRAW: longword absolute GCUBase+$164; + GCU_TRAPDIS: longword absolute GCUBase+$168; + GCU_TRAPCLR: longword absolute GCUBase+$16C; + GCU_TRAPSET: longword absolute GCUBase+$170; + + PCU_PWRSTAT: longword absolute PCUBase+$00; + PCU_PWRSET: longword absolute PCUBase+$04; + PCU_PWRCLR: longword absolute PCUBase+$08; + PCU_EVRSTAT: longword absolute PCUBase+$10; + PCU_EVRVADCSTAT: longword absolute PCUBase+$14; + PCU_PWRMON: longword absolute PCUBase+$2C; + + HCU_HDSTAT:longword absolute HCUBase+$00; + HCU_HDCLR:longword absolute HCUBase+$04; + HCU_HDSET:longword absolute HCUBase+$08; + HCU_HDCR:longword absolute HCUBase+$0C; + HCU_OSCSICTRL:longword absolute HCUBase+$14; + HCU_OSCULSTAT:longword absolute HCUBase+$18; + HCU_OSCULCTRL:longword absolute HCUBase+$1C; + + RCU_RSTSTAT: longword absolute RCUBase+$00; + RCU_RSTSET: longword absolute RCUBase+$04; + RCU_RSTCLR: longword absolute RCUBase+$08; + RCU_PRSTAT0: longword absolute RCUBase+$0C; + RCU_PRSET0: longword absolute RCUBase+$10; + RCU_PRCLR0: longword absolute RCUBase+$14; + RCU_PRSTAT1: longword absolute RCUBase+$18; + RCU_PRSET1: longword absolute RCUBase+$1C; + RCU_PRCLR1: longword absolute RCUBase+$20; + RCU_PRSTAT2: longword absolute RCUBase+$24; + RCU_PRSET2: longword absolute RCUBase+$28; + RCU_PRCLR2: longword absolute RCUBase+$2C; + RCU_PRSTAT3: longword absolute RCUBase+$30; + RCU_PRSET3: longword absolute RCUBase+$34; + RCU_PRCLR3: longword absolute RCUBase+$38; + + CCU_CLKSTAT: longword absolute CCUBase+$000; + CCU_CLKSET: longword absolute CCUBase+$004; + CCU_CLKCLR: longword absolute CCUBase+$008; + CCU_SYSCLKCR: longword absolute CCUBase+$00C; + CCU_CPUCLKCR: longword absolute CCUBase+$010; + CCU_PBCLKCR: longword absolute CCUBase+$014; + CCU_USBCLKCR: longword absolute CCUBase+$018; + CCU_EBUCLKCR: longword absolute CCUBase+$01C; + CCU_CCUCLKCR: longword absolute CCUBase+$020; + CCU_WDTCLKCR: longword absolute CCUBase+$024; + CCU_EXTCLKCR: longword absolute CCUBase+$028; + CCU_SLEEPCR: longword absolute CCUBase+$030; + CCU_DSLEEPCR: longword absolute CCUBase+$034; + CCU_OSCHPSTAT: longword absolute CCUBase+$100; + CCU_OSCHPCTRL: longword absolute CCUBase+$104; + CCU_CLKCALCONST: longword absolute CCUBase+$10C; + CCU_PLLSTAT: longword absolute CCUBase+$110; + CCU_PLLCON0: longword absolute CCUBase+$114; + CCU_PLLCON1: longword absolute CCUBase+$118; + CCU_PLLCON2: longword absolute CCUBase+$11C; + CCU_USBPLLSTAT: longword absolute CCUBase+$120; + CCU_USBPLLCON: longword absolute CCUBase+$124; + CCU_CLKMXSTAT: longword absolute CCUBase+$138; + +implementation + +procedure NMI_interrupt; external name 'NMI_interrupt'; +procedure Hardfault_interrupt; external name 'Hardfault_interrupt'; +procedure MemManage_interrupt; external name 'MemManage_interrupt'; +procedure BusFault_interrupt; external name 'BusFault_interrupt'; +procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; +procedure SWI_interrupt; external name 'SWI_interrupt'; +procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; +procedure PendingSV_interrupt; external name 'PendingSV_interrupt'; +procedure SysTick_interrupt; external name 'SysTick_interrupt'; + +procedure SCU_SR0_irq; external name 'SCU_SR0_irq'; +procedure ERU0_SR0_irq; external name 'ERU0_SR0_irq'; +procedure ERU0_SR1_irq; external name 'ERU0_SR1_irq'; +procedure ERU0_SR2_irq; external name 'ERU0_SR2_irq'; +procedure ERU0_SR3_irq; external name 'ERU0_SR3_irq'; +procedure ERU1_SR0_irq; external name 'ERU1_SR0_irq'; +procedure ERU1_SR1_irq; external name 'ERU1_SR1_irq'; +procedure ERU1_SR2_irq; external name 'ERU1_SR2_irq'; +procedure ERU1_SR3_irq; external name 'ERU1_SR3_irq'; +procedure PMU0_SR0_irq; external name 'PMU0_SR0_irq'; +procedure CADC_C0SR0_irq; external name 'CADC_C0SR0_irq'; +procedure CADC_C0SR1_irq; external name 'CADC_C0SR1_irq'; +procedure CADC_C0SR2_irq; external name 'CADC_C0SR2_irq'; +procedure CADC_C0SR3_irq; external name 'CADC_C0SR3_irq'; +procedure CADC_G0SR0_irq; external name 'CADC_G0SR0_irq'; +procedure CADC_G0SR1_irq; external name 'CADC_G0SR1_irq'; +procedure CADC_G0SR2_irq; external name 'CADC_G0SR2_irq'; +procedure CADC_G0SR3_irq; external name 'CADC_G0SR3_irq'; +procedure CADC_G1SR0_irq; external name 'CADC_G1SR0_irq'; +procedure CADC_G1SR1_irq; external name 'CADC_G1SR1_irq'; +procedure CADC_G1SR2_irq; external name 'CADC_G1SR2_irq'; +procedure CADC_G1SR3_irq; external name 'CADC_G1SR3_irq'; +procedure CADC_G2SR0_irq; external name 'CADC_G2SR0_irq'; +procedure CADC_G2SR1_irq; external name 'CADC_G2SR1_irq'; +procedure CADC_G2SR2_irq; external name 'CADC_G2SR2_irq'; +procedure CADC_G2SR3_irq; external name 'CADC_G2SR3_irq'; +procedure CADC_G3SR0_irq; external name 'CADC_G3SR0_irq'; +procedure CADC_G3SR1_irq; external name 'CADC_G3SR1_irq'; +procedure CADC_G3SR2_irq; external name 'CADC_G3SR2_irq'; +procedure CADC_G3SR3_irq; external name 'CADC_G3SR3_irq'; +procedure DSD_SRM0_irq; external name 'DSD_SRM0_irq'; +procedure DSD_SRM1_irq; external name 'DSD_SRM1_irq'; +procedure DSD_SRM2_irq; external name 'DSD_SRM2_irq'; +procedure DSD_SRM3_irq; external name 'DSD_SRM3_irq'; +procedure DSD_SRA0_irq; external name 'DSD_SRA0_irq'; +procedure DSD_SRA1_irq; external name 'DSD_SRA1_irq'; +procedure DSD_SRA2_irq; external name 'DSD_SRA2_irq'; +procedure DSD_SRA3_irq; external name 'DSD_SRA3_irq'; +procedure DAC_SR0_irq; external name 'DAC_SR0_irq'; +procedure DAC_SR1_irq; external name 'DAC_SR1_irq'; +procedure CCU40_SR0_irq; external name 'CCU40_SR0_irq'; +procedure CCU40_SR1_irq; external name 'CCU40_SR1_irq'; +procedure CCU40_SR2_irq; external name 'CCU40_SR2_irq'; +procedure CCU40_SR3_irq; external name 'CCU40_SR3_irq'; +procedure CCU41_SR0_irq; external name 'CCU41_SR0_irq'; +procedure CCU41_SR1_irq; external name 'CCU41_SR1_irq'; +procedure CCU41_SR2_irq; external name 'CCU41_SR2_irq'; +procedure CCU41_SR3_irq; external name 'CCU41_SR3_irq'; +procedure CCU42_SR0_irq; external name 'CCU42_SR0_irq'; +procedure CCU42_SR1_irq; external name 'CCU42_SR1_irq'; +procedure CCU42_SR2_irq; external name 'CCU42_SR2_irq'; +procedure CCU42_SR3_irq; external name 'CCU42_SR3_irq'; +procedure CCU43_SR0_irq; external name 'CCU43_SR0_irq'; +procedure CCU43_SR1_irq; external name 'CCU43_SR1_irq'; +procedure CCU43_SR2_irq; external name 'CCU43_SR2_irq'; +procedure CCU43_SR3_irq; external name 'CCU43_SR3_irq'; +procedure CCU80_SR0_irq; external name 'CCU80_SR0_irq'; +procedure CCU80_SR1_irq; external name 'CCU80_SR1_irq'; +procedure CCU80_SR2_irq; external name 'CCU80_SR2_irq'; +procedure CCU80_SR3_irq; external name 'CCU80_SR3_irq'; +procedure CCU81_SR0_irq; external name 'CCU81_SR0_irq'; +procedure CCU81_SR1_irq; external name 'CCU81_SR1_irq'; +procedure CCU81_SR2_irq; external name 'CCU81_SR2_irq'; +procedure CCU81_SR3_irq; external name 'CCU81_SR3_irq'; +procedure POSIF0_SR0_irq; external name 'POSIF0_SR0_irq'; +procedure POSIF0_SR1_irq; external name 'POSIF0_SR1_irq'; +procedure POSIF1_SR0_irq; external name 'POSIF1_SR0_irq'; +procedure POSIF1_SR1_irq; external name 'POSIF1_SR1_irq'; +procedure CAN_SR0_irq; external name 'CAN_SR0_irq'; +procedure CAN_SR1_irq; external name 'CAN_SR1_irq'; +procedure CAN_SR2_irq; external name 'CAN_SR2_irq'; +procedure CAN_SR3_irq; external name 'CAN_SR3_irq'; +procedure CAN_SR4_irq; external name 'CAN_SR4_irq'; +procedure CAN_SR5_irq; external name 'CAN_SR5_irq'; +procedure CAN_SR6_irq; external name 'CAN_SR6_irq'; +procedure CAN_SR7_irq; external name 'CAN_SR7_irq'; +procedure USIC0_SR0_irq; external name 'USIC0_SR0_irq'; +procedure USIC0_SR1_irq; external name 'USIC0_SR1_irq'; +procedure USIC0_SR2_irq; external name 'USIC0_SR2_irq'; +procedure USIC0_SR3_irq; external name 'USIC0_SR3_irq'; +procedure USIC0_SR4_irq; external name 'USIC0_SR4_irq'; +procedure USIC0_SR5_irq; external name 'USIC0_SR5_irq'; +procedure USIC1_SR0_irq; external name 'USIC1_SR0_irq'; +procedure USIC1_SR1_irq; external name 'USIC1_SR1_irq'; +procedure USIC1_SR2_irq; external name 'USIC1_SR2_irq'; +procedure USIC1_SR3_irq; external name 'USIC1_SR3_irq'; +procedure USIC1_SR4_irq; external name 'USIC1_SR4_irq'; +procedure USIC1_SR5_irq; external name 'USIC1_SR5_irq'; +procedure USIC2_SR0_irq; external name 'USIC2_SR0_irq'; +procedure USIC2_SR1_irq; external name 'USIC2_SR1_irq'; +procedure USIC2_SR2_irq; external name 'USIC2_SR2_irq'; +procedure USIC2_SR3_irq; external name 'USIC2_SR3_irq'; +procedure USIC2_SR4_irq; external name 'USIC2_SR4_irq'; +procedure USIC2_SR5_irq; external name 'USIC2_SR5_irq'; +procedure LEDTS0_SR0_irq; external name 'LEDTS0_SR0_irq'; +procedure FCE_SR0_irq; external name 'FCE_SR0_irq'; +procedure GPDMA0_SR0_irq; external name 'GPDMA0_SR0_irq'; +procedure SDMMC_SR0_irq; external name 'SDMMC_SR0_irq'; +procedure USB0_SR0_irq; external name 'USB0_SR0_irq'; +procedure ETH0_SR0_irq; external name 'ETH0_SR0_irq'; +procedure GPDMA1_SR0_irq; external name 'GPDMA1_SR0_irq'; + +{$define REMAP_VECTTAB} + +{$i cortexm4f_start.inc} + +procedure Vectors; assembler; nostackframe; +label interrupt_vectors; +asm + .section ".init.interrupt_vectors" +interrupt_vectors: + .long _stack_top + .long Startup + .long NMI_interrupt + .long Hardfault_interrupt + .long MemManage_interrupt + .long BusFault_interrupt + .long UsageFault_interrupt + .long 0 + .long 0 + .long 0 + .long 0 + .long SWI_interrupt + .long DebugMonitor_interrupt + .long 0 + .long PendingSV_interrupt + .long SysTick_interrupt + + .long SCU_SR0_irq + .long ERU0_SR0_irq + .long ERU0_SR1_irq + .long ERU0_SR2_irq + .long ERU0_SR3_irq + .long ERU1_SR0_irq + .long ERU1_SR1_irq + .long ERU1_SR2_irq + .long ERU1_SR3_irq + .long 0 + .long 0 + .long 0 + .long PMU0_SR0_irq + .long 0 + .long CADC_C0SR0_irq + .long CADC_C0SR1_irq + .long CADC_C0SR2_irq + .long CADC_C0SR3_irq + .long CADC_G0SR0_irq + .long CADC_G0SR1_irq + .long CADC_G0SR2_irq + .long CADC_G0SR3_irq + .long CADC_G1SR0_irq + .long CADC_G1SR1_irq + .long CADC_G1SR2_irq + .long CADC_G1SR3_irq + .long CADC_G2SR0_irq + .long CADC_G2SR1_irq + .long CADC_G2SR2_irq + .long CADC_G2SR3_irq + .long CADC_G3SR0_irq + .long CADC_G3SR1_irq + .long CADC_G3SR2_irq + .long CADC_G3SR3_irq + .long DSD_SRM0_irq + .long DSD_SRM1_irq + .long DSD_SRM2_irq + .long DSD_SRM3_irq + .long DSD_SRA0_irq + .long DSD_SRA1_irq + .long DSD_SRA2_irq + .long DSD_SRA3_irq + .long DAC_SR0_irq + .long DAC_SR1_irq + .long CCU40_SR0_irq + .long CCU40_SR1_irq + .long CCU40_SR2_irq + .long CCU40_SR3_irq + .long CCU41_SR0_irq + .long CCU41_SR1_irq + .long CCU41_SR2_irq + .long CCU41_SR3_irq + .long CCU42_SR0_irq + .long CCU42_SR1_irq + .long CCU42_SR2_irq + .long CCU42_SR3_irq + .long CCU43_SR0_irq + .long CCU43_SR1_irq + .long CCU43_SR2_irq + .long CCU43_SR3_irq + .long CCU80_SR0_irq + .long CCU80_SR1_irq + .long CCU80_SR2_irq + .long CCU80_SR3_irq + .long CCU81_SR0_irq + .long CCU81_SR1_irq + .long CCU81_SR2_irq + .long CCU81_SR3_irq + .long POSIF0_SR0_irq + .long POSIF0_SR1_irq + .long POSIF1_SR0_irq + .long POSIF1_SR1_irq + .long 0 + .long 0 + .long 0 + .long 0 + .long CAN_SR0_irq + .long CAN_SR1_irq + .long CAN_SR2_irq + .long CAN_SR3_irq + .long CAN_SR4_irq + .long CAN_SR5_irq + .long CAN_SR6_irq + .long CAN_SR7_irq + .long USIC0_SR0_irq + .long USIC0_SR1_irq + .long USIC0_SR2_irq + .long USIC0_SR3_irq + .long USIC0_SR4_irq + .long USIC0_SR5_irq + .long USIC1_SR0_irq + .long USIC1_SR1_irq + .long USIC1_SR2_irq + .long USIC1_SR3_irq + .long USIC1_SR4_irq + .long USIC1_SR5_irq + .long USIC2_SR0_irq + .long USIC2_SR1_irq + .long USIC2_SR2_irq + .long USIC2_SR3_irq + .long USIC2_SR4_irq + .long USIC2_SR5_irq + .long LEDTS0_SR0_irq + .long 0 + .long FCE_SR0_irq + .long GPDMA0_SR0_irq + .long SDMMC_SR0_irq + .long USB0_SR0_irq + .long ETH0_SR0_irq + .long 0 + .long GPDMA1_SR0_irq + + .weak NMI_interrupt + .weak Hardfault_interrupt + .weak MemManage_interrupt + .weak BusFault_interrupt + .weak UsageFault_interrupt + .weak SWI_interrupt + .weak DebugMonitor_interrupt + .weak PendingSV_interrupt + .weak SysTick_interrupt + + .weak SCU_SR0_irq + .weak ERU0_SR0_irq + .weak ERU0_SR1_irq + .weak ERU0_SR2_irq + .weak ERU0_SR3_irq + .weak ERU1_SR0_irq + .weak ERU1_SR1_irq + .weak ERU1_SR2_irq + .weak ERU1_SR3_irq + .weak PMU0_SR0_irq + .weak CADC_C0SR0_irq + .weak CADC_C0SR1_irq + .weak CADC_C0SR2_irq + .weak CADC_C0SR3_irq + .weak CADC_G0SR0_irq + .weak CADC_G0SR1_irq + .weak CADC_G0SR2_irq + .weak CADC_G0SR3_irq + .weak CADC_G1SR0_irq + .weak CADC_G1SR1_irq + .weak CADC_G1SR2_irq + .weak CADC_G1SR3_irq + .weak CADC_G2SR0_irq + .weak CADC_G2SR1_irq + .weak CADC_G2SR2_irq + .weak CADC_G2SR3_irq + .weak CADC_G3SR0_irq + .weak CADC_G3SR1_irq + .weak CADC_G3SR2_irq + .weak CADC_G3SR3_irq + .weak DSD_SRM0_irq + .weak DSD_SRM1_irq + .weak DSD_SRM2_irq + .weak DSD_SRM3_irq + .weak DSD_SRA0_irq + .weak DSD_SRA1_irq + .weak DSD_SRA2_irq + .weak DSD_SRA3_irq + .weak DAC_SR0_irq + .weak DAC_SR1_irq + .weak CCU40_SR0_irq + .weak CCU40_SR1_irq + .weak CCU40_SR2_irq + .weak CCU40_SR3_irq + .weak CCU41_SR0_irq + .weak CCU41_SR1_irq + .weak CCU41_SR2_irq + .weak CCU41_SR3_irq + .weak CCU42_SR0_irq + .weak CCU42_SR1_irq + .weak CCU42_SR2_irq + .weak CCU42_SR3_irq + .weak CCU43_SR0_irq + .weak CCU43_SR1_irq + .weak CCU43_SR2_irq + .weak CCU43_SR3_irq + .weak CCU80_SR0_irq + .weak CCU80_SR1_irq + .weak CCU80_SR2_irq + .weak CCU80_SR3_irq + .weak CCU81_SR0_irq + .weak CCU81_SR1_irq + .weak CCU81_SR2_irq + .weak CCU81_SR3_irq + .weak POSIF0_SR0_irq + .weak POSIF0_SR1_irq + .weak POSIF1_SR0_irq + .weak POSIF1_SR1_irq + .weak CAN_SR0_irq + .weak CAN_SR1_irq + .weak CAN_SR2_irq + .weak CAN_SR3_irq + .weak CAN_SR4_irq + .weak CAN_SR5_irq + .weak CAN_SR6_irq + .weak CAN_SR7_irq + .weak USIC0_SR0_irq + .weak USIC0_SR1_irq + .weak USIC0_SR2_irq + .weak USIC0_SR3_irq + .weak USIC0_SR4_irq + .weak USIC0_SR5_irq + .weak USIC1_SR0_irq + .weak USIC1_SR1_irq + .weak USIC1_SR2_irq + .weak USIC1_SR3_irq + .weak USIC1_SR4_irq + .weak USIC1_SR5_irq + .weak USIC2_SR0_irq + .weak USIC2_SR1_irq + .weak USIC2_SR2_irq + .weak USIC2_SR3_irq + .weak USIC2_SR4_irq + .weak USIC2_SR5_irq + .weak LEDTS0_SR0_irq + .weak FCE_SR0_irq + .weak GPDMA0_SR0_irq + .weak SDMMC_SR0_irq + .weak USB0_SR0_irq + .weak ETH0_SR0_irq + .weak GPDMA1_SR0_irq + + .set NMI_interrupt, HaltProc + .set Hardfault_interrupt, HaltProc + .set MemManage_interrupt, HaltProc + .set BusFault_interrupt, HaltProc + .set UsageFault_interrupt, HaltProc + .set SWI_interrupt, HaltProc + .set DebugMonitor_interrupt, HaltProc + .set PendingSV_interrupt, HaltProc + .set SysTick_interrupt, HaltProc + + .set SCU_SR0_irq, HaltProc + .set ERU0_SR0_irq, HaltProc + .set ERU0_SR1_irq, HaltProc + .set ERU0_SR2_irq, HaltProc + .set ERU0_SR3_irq, HaltProc + .set ERU1_SR0_irq, HaltProc + .set ERU1_SR1_irq, HaltProc + .set ERU1_SR2_irq, HaltProc + .set ERU1_SR3_irq, HaltProc + .set PMU0_SR0_irq, HaltProc + .set CADC_C0SR0_irq, HaltProc + .set CADC_C0SR1_irq, HaltProc + .set CADC_C0SR2_irq, HaltProc + .set CADC_C0SR3_irq, HaltProc + .set CADC_G0SR0_irq, HaltProc + .set CADC_G0SR1_irq, HaltProc + .set CADC_G0SR2_irq, HaltProc + .set CADC_G0SR3_irq, HaltProc + .set CADC_G1SR0_irq, HaltProc + .set CADC_G1SR1_irq, HaltProc + .set CADC_G1SR2_irq, HaltProc + .set CADC_G1SR3_irq, HaltProc + .set CADC_G2SR0_irq, HaltProc + .set CADC_G2SR1_irq, HaltProc + .set CADC_G2SR2_irq, HaltProc + .set CADC_G2SR3_irq, HaltProc + .set CADC_G3SR0_irq, HaltProc + .set CADC_G3SR1_irq, HaltProc + .set CADC_G3SR2_irq, HaltProc + .set CADC_G3SR3_irq, HaltProc + .set DSD_SRM0_irq, HaltProc + .set DSD_SRM1_irq, HaltProc + .set DSD_SRM2_irq, HaltProc + .set DSD_SRM3_irq, HaltProc + .set DSD_SRA0_irq, HaltProc + .set DSD_SRA1_irq, HaltProc + .set DSD_SRA2_irq, HaltProc + .set DSD_SRA3_irq, HaltProc + .set DAC_SR0_irq, HaltProc + .set DAC_SR1_irq, HaltProc + .set CCU40_SR0_irq, HaltProc + .set CCU40_SR1_irq, HaltProc + .set CCU40_SR2_irq, HaltProc + .set CCU40_SR3_irq, HaltProc + .set CCU41_SR0_irq, HaltProc + .set CCU41_SR1_irq, HaltProc + .set CCU41_SR2_irq, HaltProc + .set CCU41_SR3_irq, HaltProc + .set CCU42_SR0_irq, HaltProc + .set CCU42_SR1_irq, HaltProc + .set CCU42_SR2_irq, HaltProc + .set CCU42_SR3_irq, HaltProc + .set CCU43_SR0_irq, HaltProc + .set CCU43_SR1_irq, HaltProc + .set CCU43_SR2_irq, HaltProc + .set CCU43_SR3_irq, HaltProc + .set CCU80_SR0_irq, HaltProc + .set CCU80_SR1_irq, HaltProc + .set CCU80_SR2_irq, HaltProc + .set CCU80_SR3_irq, HaltProc + .set CCU81_SR0_irq, HaltProc + .set CCU81_SR1_irq, HaltProc + .set CCU81_SR2_irq, HaltProc + .set CCU81_SR3_irq, HaltProc + .set POSIF0_SR0_irq, HaltProc + .set POSIF0_SR1_irq, HaltProc + .set POSIF1_SR0_irq, HaltProc + .set POSIF1_SR1_irq, HaltProc + .set CAN_SR0_irq, HaltProc + .set CAN_SR1_irq, HaltProc + .set CAN_SR2_irq, HaltProc + .set CAN_SR3_irq, HaltProc + .set CAN_SR4_irq, HaltProc + .set CAN_SR5_irq, HaltProc + .set CAN_SR6_irq, HaltProc + .set CAN_SR7_irq, HaltProc + .set USIC0_SR0_irq, HaltProc + .set USIC0_SR1_irq, HaltProc + .set USIC0_SR2_irq, HaltProc + .set USIC0_SR3_irq, HaltProc + .set USIC0_SR4_irq, HaltProc + .set USIC0_SR5_irq, HaltProc + .set USIC1_SR0_irq, HaltProc + .set USIC1_SR1_irq, HaltProc + .set USIC1_SR2_irq, HaltProc + .set USIC1_SR3_irq, HaltProc + .set USIC1_SR4_irq, HaltProc + .set USIC1_SR5_irq, HaltProc + .set USIC2_SR0_irq, HaltProc + .set USIC2_SR1_irq, HaltProc + .set USIC2_SR2_irq, HaltProc + .set USIC2_SR3_irq, HaltProc + .set USIC2_SR4_irq, HaltProc + .set USIC2_SR5_irq, HaltProc + .set LEDTS0_SR0_irq, HaltProc + .set FCE_SR0_irq, HaltProc + .set GPDMA0_SR0_irq, HaltProc + .set SDMMC_SR0_irq, HaltProc + .set USB0_SR0_irq, HaltProc + .set ETH0_SR0_irq, HaltProc + .set GPDMA1_SR0_irq, HaltProc + + .text +end; + +end.