Reenabled D0-D30 registers

git-svn-id: trunk@20674 -

compiler/sparc/rspcon.inc

@@ -66,6 +66,22 @@ NR_F28 = tregister($0206001c);
 NR_F29 = tregister($0206001d);
 NR_F30 = tregister($0206001e);
 NR_F31 = tregister($0206001f);
+NR_D0 = tregister($02070000);
+NR_D2 = tregister($02070002);
+NR_D4 = tregister($02070004);
+NR_D6 = tregister($02070006);
+NR_D8 = tregister($02070008);
+NR_D10 = tregister($0207000a);
+NR_D12 = tregister($0207000c);
+NR_D14 = tregister($0207000e);
+NR_D16 = tregister($02070010);
+NR_D18 = tregister($02070012);
+NR_D20 = tregister($02070014);
+NR_D22 = tregister($02070016);
+NR_D24 = tregister($02070018);
+NR_D26 = tregister($0207001a);
+NR_D28 = tregister($0207001c);
+NR_D30 = tregister($0207001e);
 NR_C0 = tregister($03000000);
 NR_C1 = tregister($03000001);
 NR_C2 = tregister($03000002);

compiler/sparc/rspdwrf.inc

@@ -66,6 +66,22 @@
 61,
 62,
 63,
+72,
+73,
+74,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+85,
+86,
+87,
 32,
 32,
 32,

compiler/sparc/rspnor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from spreg.dat }
-139
+155

compiler/sparc/rspnum.inc

@@ -66,6 +66,22 @@ NR_F28,
 NR_F29,
 NR_F30,
 NR_F31,
+NR_D0,
+NR_D2,
+NR_D4,
+NR_D6,
+NR_D8,
+NR_D10,
+NR_D12,
+NR_D14,
+NR_D16,
+NR_D18,
+NR_D20,
+NR_D22,
+NR_D24,
+NR_D26,
+NR_D28,
+NR_D30,
 NR_C0,
 NR_C1,
 NR_C2,

compiler/sparc/rsprni.inc

@@ -98,6 +98,14 @@
 96,
 97,
 98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
 107,
 108,
 109,
@@ -106,14 +114,6 @@
 112,
 113,
 114,
-115,
-116,
-117,
-118,
-119,
-120,
-121,
-122,
 123,
 124,
 125,
@@ -130,11 +130,27 @@
 136,
 137,
 138,
-99,
+139,
-100,
+140,
-101,
+141,
-102,
+142,
-103,
+143,
-104,
+144,
-105,
+145,
-106
+146,
+147,
+148,
+149,
+150,
+151,
+152,
+153,
+154,
+115,
+116,
+117,
+118,
+119,
+120,
+121,
+122

compiler/sparc/rspsri.inc

@@ -1,37 +1,76 @@
 { don't edit, this file is generated from spreg.dat }
-107,
-108,
-117,
-118,
-119,
-120,
-121,
-122,
 123,
 124,
+133,
+134,
+135,
+136,
+137,
+138,
+139,
+140,
+141,
+142,
 125,
+143,
+144,
+145,
+146,
+147,
+148,
+149,
+150,
+151,
+152,
 126,
-109,
+153,
+154,
 127,
 128,
 129,
 130,
 131,
 132,
-133,
+83,
-134,
+84,
-135,
+93,
-136,
+94,
+95,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+85,
+103,
+104,
+105,
+106,
+107,
+108,
+109,
 110,
-137,
-138,
 111,
 112,
+86,
 113,
 114,
-115,
+87,
-116,
+88,
+89,
+90,
+91,
+92,
+118,
+117,
 67,
+72,
+73,
+74,
+75,
+76,
 68,
 77,
 78,
@@ -39,32 +78,9 @@
 80,
 81,
 82,
-83,
-84,
-85,
-86,
 69,
-87,
-88,
-89,
-90,
-91,
-92,
-93,
-94,
-95,
-96,
 70,
-97,
-98,
 71,
-72,
-73,
-74,
-75,
-76,
-102,
-101,
 35,
 36,
 45,
@@ -98,8 +114,8 @@
 43,
 44,
 33,
-100,
+116,
-99,
+115,
 1,
 2,
 3,
@@ -132,9 +148,9 @@
 14,
 15,
 16,
-103,
+119,
 34,
-104,
+120,
-105,
+121,
-106,
+122,
 0

compiler/sparc/rspstab.inc

@@ -66,6 +66,22 @@
 61,
 62,
 63,
+72,
+73,
+74,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+85,
+86,
+87,
 32,
 32,
 32,

compiler/sparc/rspstd.inc

@@ -66,6 +66,22 @@
 '%f29',
 '%f30',
 '%f31',
+'%d0',
+'%d2',
+'%d4',
+'%d6',
+'%d8',
+'%d10',
+'%d12',
+'%d14',
+'%d16',
+'%d18',
+'%d20',
+'%d22',
+'%d24',
+'%d26',
+'%d28',
+'%d30',
 '%c0',
 '%c1',
 '%c2',

compiler/sparc/rspsup.inc

@@ -66,6 +66,22 @@ RS_F28 = $1c;
 RS_F29 = $1d;
 RS_F30 = $1e;
 RS_F31 = $1f;
+RS_D0 = $00;
+RS_D2 = $02;
+RS_D4 = $04;
+RS_D6 = $06;
+RS_D8 = $08;
+RS_D10 = $0a;
+RS_D12 = $0c;
+RS_D14 = $0e;
+RS_D16 = $10;
+RS_D18 = $12;
+RS_D20 = $14;
+RS_D22 = $16;
+RS_D24 = $18;
+RS_D26 = $1a;
+RS_D28 = $1c;
+RS_D30 = $1e;
 RS_C0 = $00;
 RS_C1 = $01;
 RS_C2 = $02;

compiler/sparc/spreg.dat

@@ -75,23 +75,23 @@ F29,$02,$06,$1d,%f29,61,61
 F30,$02,$06,$1e,%f30,62,62
 F31,$02,$06,$1f,%f31,63,63
 ; Float registers, double use
-; Not enabled for now Pierre
+; Re-enabled 2012-03-30 Pierre
-; D0,$02,$07,$00,%d0,72,72
+D0,$02,$07,$00,%d0,72,72
-; D2,$02,$07,$02,%d2,73,73
+D2,$02,$07,$02,%d2,73,73
-; D4,$02,$07,$04,%d4,74,74
+D4,$02,$07,$04,%d4,74,74
-; D6,$02,$07,$06,%d6,75,75
+D6,$02,$07,$06,%d6,75,75
-; D8,$02,$07,$08,%d8,76,76
+D8,$02,$07,$08,%d8,76,76
-; D10,$02,$07,$0a,%d10,77,77
+D10,$02,$07,$0a,%d10,77,77
-; D12,$02,$07,$0c,%d12,78,78
+D12,$02,$07,$0c,%d12,78,78
-; D14,$02,$07,$0e,%d14,79,79
+D14,$02,$07,$0e,%d14,79,79
-; D16,$02,$07,$10,%d16,80,80
+D16,$02,$07,$10,%d16,80,80
-; D18,$02,$07,$12,%d18,81,81
+D18,$02,$07,$12,%d18,81,81
-; D20,$02,$07,$14,%d20,82,82
+D20,$02,$07,$14,%d20,82,82
-; D22,$02,$07,$16,%d22,83,83
+D22,$02,$07,$16,%d22,83,83
-; D24,$02,$07,$18,%d24,84,84
+D24,$02,$07,$18,%d24,84,84
-; D26,$02,$07,$1a,%d26,85,85
+D26,$02,$07,$1a,%d26,85,85
-; D28,$02,$07,$1c,%d28,86,86
+D28,$02,$07,$1c,%d28,86,86
-; D30,$02,$07,$1e,%d30,87,87
+D30,$02,$07,$1e,%d30,87,87
 
 
 ; Coprocessor registers