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+ support for nop, msr and mrs instructions

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git-svn-id: trunk@12609 -
This commit is contained in:
florian 2009-01-26 14:18:42 +00:00
parent 7cb26b37a1
commit c5816c500a
6 changed files with 46 additions and 7 deletions
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3
compiler/arm/armatt.inc
View File

@ -47,11 +47,14 @@
'mcr',
'mla',
'mov',
'mrs',
'msr',
'mnf',
'muf',
'mul',
'mvf',
'mvn',
'nop',
'orr',
'rdf',
'rfs',

3
compiler/arm/armatts.inc
View File

@ -174,5 +174,8 @@ attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE
);

14
compiler/arm/armins.dat
View File

@ -246,13 +246,13 @@ reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
; [MRC]
; reg32,reg32 \321\301\1\x13\110 ARM7
; [MRScc]
; reg32,reg32 \x10\x01\x0F ARM7
[MRScc]
reg32,reg32 \x10\x01\x0F ARM7
; [MSRcc]
; reg32,reg32 \x11\x01\x29\xF0 ARM7
; regf,reg32 \x12\x01\x28\xF0 ARM7
; regf,imm \x13\x03\x28\xF0 ARM7
[MSRcc]
reg32,reg32 \x11\x01\x29\xF0 ARM7
regf,reg32 \x12\x01\x28\xF0 ARM7
regf,imm \x13\x03\x28\xF0 ARM7
[MNFcc]
@ -271,6 +271,8 @@ fpureg,immfpu \xF2 FPA
; reg32,reg32,imm \xA\x1\xE0 ARM7
; reg32,imm \xB\x3\xE0 ARM7
[NOP]
[ORRcc]
reg32,reg32,reg32 \4\x1\x80 ARM7
reg32,reg32,reg32,reg32 \5\x1\x80 ARM7

2
compiler/arm/armnop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat }
102;
106;

3
compiler/arm/armop.inc
View File

@ -47,11 +47,14 @@ A_LOG,
A_MCR,
A_MLA,
A_MOV,
A_MRS,
A_MSR,
A_MNF,
A_MUF,
A_MUL,
A_MVF,
A_MVN,
A_NOP,
A_ORR,
A_RDF,
A_RFS,

28
compiler/arm/armtab.inc
View File

@ -399,6 +399,34 @@
code : #21#0#32#144;
flags : if_arm7
),
(
opcode : A_MRS;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #16#1#15;
flags : if_arm7
),
(
opcode : A_MSR;
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
code : #17#1#41#240;
flags : if_arm7
),
(
opcode : A_MSR;
ops : 2;
optypes : (ot_regf,ot_reg32,ot_none,ot_none);
code : #18#1#40#240;
flags : if_arm7
),
(
opcode : A_MSR;
ops : 2;
optypes : (ot_regf,ot_immediate,ot_none,ot_none);
code : #19#3#40#240;
flags : if_arm7
),
(
opcode : A_MUL;
ops : 3;