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https://gitlab.com/freepascal.org/fpc/source.git
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* optimized spilling writing when the reg operand can be
replaced by reference
This commit is contained in:
peter
parent
044ec56b56
commit
c853d10cc2
@ -105,388 +105,6 @@ implementation
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Trgcpu
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******************************************************************************}
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{$ifdef OLDRGX86}
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function trgx86.instr_spill_register(list:Taasmoutput;
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instr:taicpu;
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const r:Tsuperregisterset;
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const spilltemplist:Tspill_temp_list): boolean;
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{
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Spill the registers in r in this instruction. Returns true if any help
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registers are used. This procedure has become one big hack party, because
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of the huge amount of situations you can have. The irregularity of the i386
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instruction set doesn't help either. (DM)
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}
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var i:byte;
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supreg:Tsuperregister;
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subreg:Tsubregister;
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helpreg:Tregister;
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helpins:Taicpu;
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op:Tasmop;
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hopsize:Topsize;
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pos:Tai;
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begin
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{Situation examples are in intel notation, so operand order:
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mov eax , ebx
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^^^ ^^^
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oper[1] oper[0]
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(DM)}
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result:=false;
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with taicpu(instr) do
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begin
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case ops of
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0:
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;
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1:
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begin
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if (oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[0]^.reg);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push r20d ; r20d must be spilled into [ebp-12]
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Change into:
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push [ebp-12] ; Replace register by reference }
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{ hopsize:=reg2opsize(oper[0].reg);}
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oper[0]^.typ:=top_ref;
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new(oper[0]^.ref);
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oper[0]^.ref^:=spilltemplist[supreg];
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{ oper[0]^.ref^.size:=hopsize;}
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end;
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end;
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if oper[0]^.typ=top_ref then
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begin
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supreg:=getsupreg(oper[0]^.ref^.base);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push [r21d+4*r22d] ; r21d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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push [r23d+4*r22d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[0]^.ref^.base);
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if oper[0]^.ref^.index=NR_NO then
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pos:=Tai(previous)
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else
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pos:=get_insert_pos(Tai(previous),getsupreg(oper[0]^.ref^.index),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.ref^.base),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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oper[0]^.ref^.base:=helpreg;
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end;
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supreg:=getsupreg(oper[0]^.ref^.index);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push [r21d+4*r22d] ; r22d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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push [r21d+4*r23d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[0]^.ref^.index);
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if oper[0]^.ref^.base=NR_NO then
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pos:=Tai(instr.previous)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.ref^.base),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.ref^.index),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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oper[0]^.ref^.index:=helpreg;
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end;
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end;
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end;
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2,
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3 :
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begin
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{ Opcodes with 3 registers are shrd/shld, where the 3rd operand is const or CL,
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that doesn't need spilling }
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{ First spill the registers from the references. This is
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required because the reference can be moved from this instruction
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to a MOV instruction when spilling of the register operand is done }
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for i:=0 to 1 do
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if oper[i]^.typ=top_ref then
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begin
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supreg:=getsupreg(oper[i]^.ref^.base);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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add r20d,[r21d+4*r22d] ; r21d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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add r20d,[r23d+4*r22d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[i]^.ref^.base);
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if i=1 then
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.index),getsupreg(oper[0]^.reg),RS_INVALID)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.index),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[i]^.ref^.base),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[i]^.ref^.base:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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supreg:=getsupreg(oper[i]^.ref^.index);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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add r20d,[r21d+4*r22d] ; r22d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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add r20d,[r21d+4*r23d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[i]^.ref^.index);
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if i=1 then
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.base),
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getsupreg(oper[0]^.reg),RS_INVALID)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.base),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[i]^.ref^.index),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[i]^.ref^.index:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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end;
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if (oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[0]^.reg);
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subreg:=getsubreg(oper[0]^.reg);
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if supregset_in(r,supreg) then
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if oper[1]^.typ=top_ref then
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begin
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{Situation example:
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add [r20d],r21d ; r21d must be spilled into [ebp-12]
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Change into:
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mov r22d,[ebp-12] ; Use a help register
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add [r20d],r22d ; Replace register by helpregister }
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.reg),
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getsupreg(oper[1]^.ref^.base),getsupreg(oper[1]^.ref^.index));
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.reg),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end
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else
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begin
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{Situation example:
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add r20d,r21d ; r21d must be spilled into [ebp-12]
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Change into:
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add r20d,[ebp-12] ; Replace register by reference }
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oper[0]^.typ:=top_ref;
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new(oper[0]^.ref);
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oper[0]^.ref^:=spilltemplist[supreg];
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end;
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end;
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if (oper[1]^.typ=top_reg) and
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(getregtype(oper[1]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[1]^.reg);
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subreg:=getsubreg(oper[1]^.reg);
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if supregset_in(r,supreg) then
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begin
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if oper[0]^.typ=top_ref then
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begin
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{Situation example:
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add r20d,[r21d] ; r20d must be spilled into [ebp-12]
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Change into:
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mov r22d,[r21d] ; Use a help register
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add [ebp-12],r22d ; Replace register by helpregister }
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.ref^.base),
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getsupreg(oper[0]^.ref^.index),RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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op:=A_MOV;
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hopsize:=opsize; {Save old value...}
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if (opcode=A_MOVZX) or (opcode=A_MOVSX) or (opcode=A_LEA) then
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begin
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{Because 'movzx memory,register' does not exist...}
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op:=opcode;
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opcode:=A_MOV;
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opsize:=reg2opsize(oper[1]^.reg);
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end;
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helpins:=Taicpu.op_ref_reg(op,hopsize,oper[0]^.ref^,helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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dispose(oper[0]^.ref);
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oper[0]^.typ:=top_reg;
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oper[0]^.reg:=helpreg;
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oper[1]^.typ:=top_ref;
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new(oper[1]^.ref);
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oper[1]^.ref^:=spilltemplist[supreg];
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end
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else
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begin
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{Situation example:
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add r20d,r21d ; r20d must be spilled into [ebp-12]
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Change into:
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add [ebp-12],r21d ; Replace register by reference }
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if (opcode=A_MOVZX) or (opcode=A_MOVSX) then
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begin
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{Because 'movzx memory,register' does not exist...}
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result:=true;
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op:=opcode;
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hopsize:=opsize;
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opcode:=A_MOV;
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opsize:=reg2opsize(oper[1]^.reg);
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.reg),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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helpins:=Taicpu.op_reg_reg(op,hopsize,oper[0]^.reg,helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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oper[1]^.typ:=top_ref;
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new(oper[1]^.ref);
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oper[1]^.ref^:=spilltemplist[supreg];
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end;
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end;
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end;
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{ The i386 instruction set never gets boring...
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some opcodes do not support a memory location as destination }
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if (oper[1]^.typ=top_ref) and
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(
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(oper[0]^.typ=top_const) or
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((oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype))
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) then
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begin
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case opcode of
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A_SHLD,A_SHRD,
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A_IMUL :
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begin
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{Yikes! We just changed the destination register into
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a memory location above here.
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Situation examples:
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imul [ebp-12],r21d ; We need a help register
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imul [ebp-12],<const> ; We need a help register
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Change into:
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mov r22d,[ebp-12] ; Use a help instruction (only for IMUL)
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imul r22d,r21d ; Replace reference by helpregister
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mov [ebp-12],r22d ; Use another help instruction}
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getregisterinline(list,Tai(previous),subreg,helpreg);
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result:=true;
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{First help instruction.}
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helpins:=Taicpu.op_ref_reg(A_MOV,opsize,oper[1]^.ref^,helpreg);
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if previous=nil then
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list.insert(helpins)
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else
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list.insertafter(helpins,previous);
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{Second help instruction.}
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helpins:=Taicpu.op_reg_ref(A_MOV,opsize,helpreg,oper[1]^.ref^);
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dispose(oper[1]^.ref);
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oper[1]^.typ:=top_reg;
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oper[1]^.reg:=helpreg;
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list.insertafter(helpins,instr);
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ungetregisterinline(list,instr,helpreg);
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end;
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end;
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end;
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{ The i386 instruction set never gets boring...
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some opcodes do not support a memory location as source }
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if (oper[0]^.typ=top_ref) and
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(oper[1]^.typ=top_reg) and
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(getregtype(oper[1]^.reg)=regtype) then
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begin
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case opcode of
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A_BT,A_BTS,
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A_BTC,A_BTR :
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begin
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{Yikes! We just changed the source register into
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a memory location above here.
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Situation example:
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bt r21d,[ebp-12] ; We need a help register
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Change into:
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mov r22d,[ebp-12] ; Use a help instruction (only for IMUL)
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bt r21d,r22d ; Replace reference by helpregister}
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getregisterinline(list,Tai(previous),subreg,helpreg);
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result:=true;
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{First help instruction.}
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helpins:=Taicpu.op_ref_reg(A_MOV,opsize,oper[0]^.ref^,helpreg);
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if previous=nil then
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list.insert(helpins)
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else
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list.insertafter(helpins,previous);
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dispose(oper[0]^.ref);
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oper[0]^.typ:=top_reg;
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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end;
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end;
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end;
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end;
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else
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internalerror(200409202);
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end;
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end;
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end;
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{$endif OLDRGX86}
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function trgx86.get_spill_subreg(r : tregister) : tsubregister;
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begin
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result:=getsubreg(r);
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@ -494,8 +112,80 @@ implementation
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function trgx86.do_spill_replace(list:Taasmoutput;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;
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var
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replaceoper : longint;
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begin
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result:=false;
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with instr do
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begin
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replaceoper:=-1;
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case ops of
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1 :
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begin
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if (oper[0]^.typ=top_reg) then
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begin
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if getsupreg(oper[0]^.reg)<>orgreg then
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internalerror(200410101);
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replaceoper:=0;
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end;
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end;
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2,3 :
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begin
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{ We can handle opcodes with 2 and 3 operands the same way. The opcodes
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with 3 registers are shrd/shld, where the 3rd operand is const or CL,
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that doesn't need spilling }
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if (oper[0]^.typ=top_reg) and
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(oper[1]^.typ=top_reg) and
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(getsupreg(oper[0]^.reg)<>getsupreg(oper[1]^.reg)) then
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begin
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{ One of the arguments shall be able to be replaced }
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if (getregtype(oper[0]^.reg)=regtype) and
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(getsupreg(oper[0]^.reg)=orgreg) then
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replaceoper:=0
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else
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if (getregtype(oper[0]^.reg)=regtype) and
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(getsupreg(oper[1]^.reg)=orgreg) then
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replaceoper:=1
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else
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internalerror(200410101);
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case replaceoper of
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0 :
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begin
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{ Some instructions don't allow memory references
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for source }
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case instr.opcode of
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A_BT,
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A_BTS,
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A_BTC,
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A_BTR :
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replaceoper:=-1;
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end;
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end;
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1 :
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begin
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{ Some instructions don't allow memory references
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for destination }
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case instr.opcode of
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A_SHLD,
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A_SHRD,
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A_IMUL :
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replaceoper:=-1;
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end;
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end;
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end;
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end;
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end;
|
||||
end;
|
||||
|
||||
{ Replace register with spill reference }
|
||||
if replaceoper<>-1 then
|
||||
begin
|
||||
oper[replaceoper]^.typ:=top_ref;
|
||||
new(oper[replaceoper]^.ref);
|
||||
oper[replaceoper]^.ref^:=spilltemp;
|
||||
result:=true;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -625,7 +315,11 @@ implementation
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.8 2004-10-05 20:41:02 peter
|
||||
Revision 1.9 2004-10-10 16:30:26 peter
|
||||
* optimized spilling writing when the reg operand can be
|
||||
replaced by reference
|
||||
|
||||
Revision 1.8 2004/10/05 20:41:02 peter
|
||||
* more spilling rewrites
|
||||
|
||||
Revision 1.7 2004/10/04 20:46:22 peter
|
||||
|
||||
Loading…
Reference in New Issue
Block a user