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* x86: Flags that relate to optimization hints rather than features have been moved to a separate set
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
9b58545fb7
commit
c9461b7313
@ -167,11 +167,7 @@ Const
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type
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tcpuflags =
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(CPUX86_HAS_BTX, { Bit-test instructions (BT, BTC, BTR and BTS) are available }
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CPUX86_HAS_FAST_XCHG, { XCHG %reg,%reg executes in 2 cycles or less }
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CPUX86_HAS_CMOV, { CMOVcc instructions are available }
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CPUX86_HAS_FAST_BTX, { BT/C/R/S instructions with register operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BT_MEM, { BT instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BTX_MEM, { BTC/R/S instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_SSEUNIT, { SSE instructions are available }
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CPUX86_HAS_SSE2, { SSE2 instructions are available }
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CPUX86_HAS_BMI1, { BMI1 instructions are available }
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@ -190,20 +186,33 @@ type
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FPUX86_HAS_AVX512DQ
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);
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{ Instruction optimisation hints }
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TCPUOptimizeFlags =
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(CPUX86_HINT_FAST_BT_REG_IMM, { BT instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_REG_REG, { BT instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_REG_IMM, { BTC/R/S instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_REG_REG, { BTC/R/S instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BT_MEM_IMM, { BT instructions with memory sources and inmediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_MEM_REG, { BT instructions with memory sources and register indices and a register index are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_IMM, { BTC/R/S instructions with memory sources and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_REG, { BTC/R/S instructions with memory sources and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_XCHG { XCHG %reg,%reg executes in 2 cycles or less }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags = (
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{ cpu_none } [],
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{ cpu_386 } [CPUX86_HAS_BTX],
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{ cpu_486 } [CPUX86_HAS_BTX],
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{ cpu_Pentium } [CPUX86_HAS_BTX],
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{ cpu_Pentium2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX],
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{ cpu_Pentium3 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT],
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{ cpu_Pentium4 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_PentiumM } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_core_i } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx2 } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_FAST_BT_MEM,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
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{ cpu_Pentium2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV],
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{ cpu_Pentium3 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT],
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{ cpu_Pentium4 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_PentiumM } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_core_i } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
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);
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fpu_capabilities : array[tfputype] of set of tfpuflags = (
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@ -220,6 +229,21 @@ type
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{ fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
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);
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cpu_optimization_hints : array[TCPUType] of set of TCPUOptimizeFlags = (
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{ cpu_none } [],
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{ cpu_386 } [],
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{ cpu_486 } [],
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{ cpu_Pentium } [],
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{ cpu_Pentium2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_Pentium3 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_Pentium4 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_PentiumM } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_i } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_avx } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_avx2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_zen } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG]
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);
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Implementation
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end.
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@ -156,15 +156,24 @@ Const
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type
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tcpuflags =
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(CPUX86_HAS_BTX, { Bit-test instructions (BT, BTC, BTR and BTS) are available }
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CPUX86_HAS_FAST_XCHG, { XCHG %reg,%reg executes in 2 cycles or less }
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CPUX86_HAS_CMOV, { CMOVcc instructions are available }
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CPUX86_HAS_FAST_BTX, { BT/C/R/S instructions with register operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BT_MEM, { BT instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BTX_MEM, { BTC/R/S instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_SSEUNIT, { SSE instructions are available }
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CPUX86_HAS_SSE2 { SSE2 instructions are available }
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);
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{ Instruction optimisation hints }
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TCPUOptimizeFlags =
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(CPUX86_HINT_FAST_BT_REG_IMM, { BT instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_REG_REG, { BT instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_REG_IMM, { BTC/R/S instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_REG_REG, { BTC/R/S instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BT_MEM_IMM, { BT instructions with memory sources and inmediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_MEM_REG, { BT instructions with memory sources and register indices and a register index are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_IMM, { BTC/R/S instructions with memory sources and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_REG, { BTC/R/S instructions with memory sources and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_XCHG { XCHG %reg,%reg executes in 2 cycles or less }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags = (
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{ cpu_none } [],
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@ -174,10 +183,24 @@ type
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{ cpu_386 } [CPUX86_HAS_BTX],
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{ cpu_486 } [CPUX86_HAS_BTX],
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{ cpu_Pentium } [CPUX86_HAS_BTX],
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{ cpu_Pentium2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX],
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{ cpu_Pentium3 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT],
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{ cpu_Pentium4 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_PentiumM } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2]
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{ cpu_Pentium2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV],
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{ cpu_Pentium3 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT],
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{ cpu_Pentium4 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_PentiumM } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2]
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);
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cpu_optimization_hints : array[TCPUType] of set of TCPUOptimizeFlags = (
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{ cpu_none } [],
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{ cpu_8086 } [],
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{ cpu_186 } [],
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{ cpu_286 } [],
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{ cpu_386 } [],
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{ cpu_486 } [],
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{ cpu_Pentium } [],
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{ cpu_Pentium2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_Pentium3 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_Pentium4 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_PentiumM } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG]
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);
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x86_near_code_models = [mm_tiny,mm_small,mm_compact];
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@ -8614,7 +8614,7 @@ unit aoptx86;
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{ From the Pentium M onwards, XCHG only has a latency of 2 rather
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than 3, so it becomes a saving compared to three MOVs with two of
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them able to execute simultaneously. [Kit] }
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(CPUX86_HAS_FAST_XCHG in cpu_capabilities[current_settings.optimizecputype]);
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(CPUX86_HINT_FAST_XCHG in cpu_optimization_hints[current_settings.optimizecputype]);
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end;
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var
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@ -168,11 +168,7 @@ Const
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type
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tcpuflags =
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(CPUX86_HAS_BTX, { Bit-test instructions (BT, BTC, BTR and BTS) are available }
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CPUX86_HAS_FAST_XCHG, { XCHG %reg,%reg executes in 2 cycles or less }
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CPUX86_HAS_CMOV, { CMOVcc instructions are available }
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CPUX86_HAS_FAST_BTX, { BT/C/R/S instructions with register operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BT_MEM, { BT instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_FAST_BTX_MEM, { BTC/R/S instructions with memory operands are at least as fast as logical instructions }
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CPUX86_HAS_SSEUNIT, { SSE instructions are available }
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CPUX86_HAS_SSE2, { SSE2 instructions are available }
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CPUX86_HAS_BMI1, { BMI1 instructions are available }
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@ -192,14 +188,27 @@ type
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FPUX86_HAS_AVX512DQ
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);
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{ Instruction optimisation hints }
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TCPUOptimizeFlags =
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(CPUX86_HINT_FAST_BT_REG_IMM, { BT instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_REG_REG, { BT instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_REG_IMM, { BTC/R/S instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_REG_REG, { BTC/R/S instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BT_MEM_IMM, { BT instructions with memory sources and inmediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_MEM_REG, { BT instructions with memory sources and register indices and a register index are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_IMM, { BTC/R/S instructions with memory sources and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_REG, { BTC/R/S instructions with memory sources and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_XCHG { XCHG %reg,%reg executes in 2 cycles or less }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags = (
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{ cpu_none } [],
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{ Athlon64 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_core_i } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx2 } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen } [CPUX86_HAS_BTX,CPUX86_HAS_FAST_XCHG,CPUX86_HAS_CMOV,CPUX86_HAS_FAST_BTX,CPUX86_HAS_FAST_BT_MEM,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
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{ Athlon64 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_core_i } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
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{ cpu_core_avx2 } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen } [CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
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);
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fpu_capabilities : array[tfputype] of set of tfpuflags = (
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@ -214,6 +223,15 @@ type
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{ fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA,FPUX86_HAS_32MMREGS,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
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);
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cpu_optimization_hints : array[TCPUType] of set of TCPUOptimizeFlags = (
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{ cpu_none } [],
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{ cpu_Athlon64 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_i } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_avx } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_core_avx2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG],
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{ cpu_zen } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG]
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);
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Implementation
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end.
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