From c9f8703679432ca665a5d9bfcbfbb05193491cee Mon Sep 17 00:00:00 2001 From: nickysn Date: Thu, 1 May 2014 21:18:47 +0000 Subject: [PATCH] + set ref.segment to NR_SS for all temps/localvars on i8086. This allows the segment to survive e.g. several nested vecnodes, which cause the base register to change from BP to something else. In the cases where the ss: prefix is not needed, it is removed by make_simple_ref. + remove the ss: prefix in the several cases where make_simple_ref isn't called (namely spilling and tcg8086.a_call_reg_far) git-svn-id: trunk@27714 - --- .gitattributes | 1 + compiler/i8086/cgcpu.pas | 1 + compiler/i8086/cpunode.pas | 2 +- compiler/i8086/rgcpu.pas | 23 +++++++++++---- compiler/i8086/tgcpu.pas | 58 ++++++++++++++++++++++++++++++++++++++ compiler/ppc8086.lpi | 9 +++++- compiler/x86/aasmcpu.pas | 36 ++++++++++++++--------- 7 files changed, 109 insertions(+), 21 deletions(-) create mode 100644 compiler/i8086/tgcpu.pas diff --git a/.gitattributes b/.gitattributes index 0bfe5710f2..7fc29d16d4 100644 --- a/.gitattributes +++ b/.gitattributes @@ -282,6 +282,7 @@ compiler/i8086/ra8086att.pas svneol=native#text/plain compiler/i8086/ra8086int.pas svneol=native#text/plain compiler/i8086/rgcpu.pas svneol=native#text/plain compiler/i8086/symcpu.pas svneol=native#text/plain +compiler/i8086/tgcpu.pas svneol=native#text/plain compiler/ia64/aasmcpu.pas svneol=native#text/plain compiler/ia64/cpubase.pas svneol=native#text/plain compiler/ia64/cpuinfo.pas svneol=native#text/plain diff --git a/compiler/i8086/cgcpu.pas b/compiler/i8086/cgcpu.pas index 88fa45ea8d..d18418efbf 100644 --- a/compiler/i8086/cgcpu.pas +++ b/compiler/i8086/cgcpu.pas @@ -246,6 +246,7 @@ unit cgcpu; a_load_reg_ref(list,OS_32,OS_32,reg,href); cg.getcpuregister(list,NR_BX); cg.getcpuregister(list,NR_SI); + href.segment:=NR_NO; list.concat(taicpu.op_ref(A_CALL,S_FAR,href)); tg.ungettemp(list,href); end; diff --git a/compiler/i8086/cpunode.pas b/compiler/i8086/cpunode.pas index d66522b1a8..59208c5b8b 100644 --- a/compiler/i8086/cpunode.pas +++ b/compiler/i8086/cpunode.pas @@ -57,7 +57,7 @@ unit cpunode; n8086mat, n8086con, { these are not really nodes } - n8086tcon, + n8086tcon,tgcpu, { symtable } symcpu ; diff --git a/compiler/i8086/rgcpu.pas b/compiler/i8086/rgcpu.pas index becac48aca..2924799ab6 100644 --- a/compiler/i8086/rgcpu.pas +++ b/compiler/i8086/rgcpu.pas @@ -30,11 +30,15 @@ unit rgcpu; uses cpubase, cpuinfo, - aasmbase,aasmtai,aasmdata, - cclasses,globtype,cgbase,rgobj,rgx86; + aasmbase,aasmtai,aasmdata,aasmcpu, + cclasses,globtype,cgbase,cgutils,rgobj,rgx86; type + + { trgcpu } + trgcpu = class(trgx86) + function do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;override; procedure add_constraints(reg:Tregister);override; end; @@ -47,9 +51,7 @@ implementation uses systems, - verbose, - aasmcpu, - cgutils; + verbose; const { This value is used in tsaved. If the array value is equal @@ -60,6 +62,17 @@ implementation trgcpu *************************************************************************} + function trgcpu.do_spill_replace(list: TAsmList; instr: taicpu; orgreg: tsuperregister; const spilltemp: treference): boolean; + var + spilltemp2: treference; + begin + spilltemp2:=spilltemp; + if spilltemp2.segment=NR_SS then + spilltemp2.segment:=NR_NO; + Result:=inherited do_spill_replace(list, instr, orgreg, spilltemp2); + end; + + procedure trgcpu.add_constraints(reg:Tregister); var supreg : tsuperregister; diff --git a/compiler/i8086/tgcpu.pas b/compiler/i8086/tgcpu.pas new file mode 100644 index 0000000000..c5dda4fdcc --- /dev/null +++ b/compiler/i8086/tgcpu.pas @@ -0,0 +1,58 @@ +{ + Copyright (C) 1998-2000 by Florian Klaempfl + + This unit handles the temporary variables stuff for i8086 + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + **************************************************************************** +} +{ + This unit handles the temporary variables stuff for i8086. +} +unit tgcpu; + +{$i fpcdefs.inc} + + interface + + uses + tgobj,globtype,aasmdata,cgutils,symtype; + + type + + { ttgi8086 } + + ttgi8086 = class(ttgobj) + protected + procedure alloctemp(list: TAsmList; size,alignment : longint; temptype : ttemptype; def:tdef; out ref: treference);override; + end; + +implementation + +uses + cpubase; + +{ ttgi8086 } + +procedure ttgi8086.alloctemp(list: TAsmList; size, alignment: longint; temptype: ttemptype; def: tdef; out ref: treference); + begin + inherited; + ref.segment:=NR_SS; + end; + +begin + tgobjclass:=ttgi8086; +end. diff --git a/compiler/ppc8086.lpi b/compiler/ppc8086.lpi index abe0c1015f..1398cb8abc 100644 --- a/compiler/ppc8086.lpi +++ b/compiler/ppc8086.lpi @@ -28,7 +28,7 @@ - + @@ -578,6 +578,7 @@ + @@ -984,6 +985,7 @@ + @@ -1043,6 +1045,11 @@ + + + + + diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index e0b9f30425..95be42d058 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -3084,10 +3084,14 @@ implementation var tmpref: treference; begin + tmpref:=ref; +{$ifdef i8086} + if tmpref.segment=NR_SS then + tmpref.segment:=NR_NO; +{$endif i8086} case getregtype(r) of R_INTREGISTER : begin - tmpref:=ref; if getsubreg(r)=R_SUBH then inc(tmpref.offset); { we don't need special code here for 32 bit loads on x86_64, since @@ -3098,24 +3102,24 @@ implementation if current_settings.fputype in fpu_avx_instructionsets then case getsubreg(r) of R_SUBMMD: - result:=taicpu.op_ref_reg(A_VMOVSD,reg2opsize(r),ref,r); + result:=taicpu.op_ref_reg(A_VMOVSD,reg2opsize(r),tmpref,r); R_SUBMMS: - result:=taicpu.op_ref_reg(A_VMOVSS,reg2opsize(r),ref,r); + result:=taicpu.op_ref_reg(A_VMOVSS,reg2opsize(r),tmpref,r); R_SUBQ, R_SUBMMWHOLE: - result:=taicpu.op_ref_reg(A_VMOVQ,S_NO,ref,r); + result:=taicpu.op_ref_reg(A_VMOVQ,S_NO,tmpref,r); else internalerror(200506043); end else case getsubreg(r) of R_SUBMMD: - result:=taicpu.op_ref_reg(A_MOVSD,reg2opsize(r),ref,r); + result:=taicpu.op_ref_reg(A_MOVSD,reg2opsize(r),tmpref,r); R_SUBMMS: - result:=taicpu.op_ref_reg(A_MOVSS,reg2opsize(r),ref,r); + result:=taicpu.op_ref_reg(A_MOVSS,reg2opsize(r),tmpref,r); R_SUBQ, R_SUBMMWHOLE: - result:=taicpu.op_ref_reg(A_MOVQ,S_NO,ref,r); + result:=taicpu.op_ref_reg(A_MOVQ,S_NO,tmpref,r); else internalerror(200506043); end; @@ -3130,10 +3134,14 @@ implementation size: topsize; tmpref: treference; begin + tmpref:=ref; +{$ifdef i8086} + if tmpref.segment=NR_SS then + tmpref.segment:=NR_NO; +{$endif i8086} case getregtype(r) of R_INTREGISTER : begin - tmpref:=ref; if getsubreg(r)=R_SUBH then inc(tmpref.offset); size:=reg2opsize(r); @@ -3152,24 +3160,24 @@ implementation if current_settings.fputype in fpu_avx_instructionsets then case getsubreg(r) of R_SUBMMD: - result:=taicpu.op_reg_ref(A_VMOVSD,reg2opsize(r),r,ref); + result:=taicpu.op_reg_ref(A_VMOVSD,reg2opsize(r),r,tmpref); R_SUBMMS: - result:=taicpu.op_reg_ref(A_VMOVSS,reg2opsize(r),r,ref); + result:=taicpu.op_reg_ref(A_VMOVSS,reg2opsize(r),r,tmpref); R_SUBQ, R_SUBMMWHOLE: - result:=taicpu.op_reg_ref(A_VMOVQ,S_NO,r,ref); + result:=taicpu.op_reg_ref(A_VMOVQ,S_NO,r,tmpref); else internalerror(200506042); end else case getsubreg(r) of R_SUBMMD: - result:=taicpu.op_reg_ref(A_MOVSD,reg2opsize(r),r,ref); + result:=taicpu.op_reg_ref(A_MOVSD,reg2opsize(r),r,tmpref); R_SUBMMS: - result:=taicpu.op_reg_ref(A_MOVSS,reg2opsize(r),r,ref); + result:=taicpu.op_reg_ref(A_MOVSS,reg2opsize(r),r,tmpref); R_SUBQ, R_SUBMMWHOLE: - result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,ref); + result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,tmpref); else internalerror(200506042); end;