From ca29df1aa9c58b951d8e2dbaa7b98a4e56563f3e Mon Sep 17 00:00:00 2001 From: florian Date: Fri, 27 May 2022 23:31:28 +0200 Subject: [PATCH] * Risc-V: return with mret from interrupt handlers, resolves #39737 --- compiler/riscv32/cgcpu.pas | 7 ++++++- compiler/riscv64/cgcpu.pas | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/compiler/riscv32/cgcpu.pas b/compiler/riscv32/cgcpu.pas index d7d3751ff1..48effea81a 100644 --- a/compiler/riscv32/cgcpu.pas +++ b/compiler/riscv32/cgcpu.pas @@ -323,7 +323,12 @@ unit cgcpu; end; end; - list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG)); + if po_interrupt in current_procinfo.procdef.procoptions then + begin + list.concat(Taicpu.Op_none(A_MRET)); + end + else + list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG)); end; diff --git a/compiler/riscv64/cgcpu.pas b/compiler/riscv64/cgcpu.pas index a39329fc28..d2b6523629 100644 --- a/compiler/riscv64/cgcpu.pas +++ b/compiler/riscv64/cgcpu.pas @@ -513,7 +513,12 @@ implementation end; end; - list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG)); + if po_interrupt in current_procinfo.procdef.procoptions then + begin + list.concat(Taicpu.Op_none(A_MRET)); + end + else + list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG)); end;