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@ -0,0 +1,450 @@
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{
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Copyright (c) 1998-2012 by Florian Klaempfl and Peter Vreman
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Contains the base types for ARM64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{ Base unit for processor information. This unit contains
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enumerations of registers, opcodes, sizes, and other
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such things which are processor specific.
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}
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unit cpubase;
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{$define USEINLINE}
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{$i fpcdefs.inc}
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interface
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uses
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cutils,cclasses,
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globtype,globals,
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cpuinfo,
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aasmbase,
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cgbase
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;
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{*****************************************************************************
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Assembler Opcodes
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*****************************************************************************}
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type
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TAsmOp= {$i a64op.inc}
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{ This should define the array of instructions as string }
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op2strtable=array[tasmop] of string[11];
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const
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{ First value of opcode enumeration }
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firstop = low(tasmop);
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{ Last value of opcode enumeration }
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lastop = high(tasmop);
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{*****************************************************************************
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Registers
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*****************************************************************************}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i ra64nor.inc}-1;
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const
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{ Available Superregisters }
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{$i ra64sup.inc}
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R_SUBWHOLE = R_SUBQ;
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{ Available Registers }
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{$i ra64con.inc}
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{ Integer Super registers first and last }
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first_int_supreg = RS_X0;
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first_int_imreg = $20;
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{ Integer Super registers first and last }
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first_fpu_supreg = RS_S0;
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first_fpu_imreg = $20;
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{ MM Super register first and last }
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first_mm_supreg = RS_S0;
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first_mm_imreg = $20;
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{ TODO: Calculate bsstart}
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regnumber_count_bsstart = 64;
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regnumber_table : array[tregisterindex] of tregister = (
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{$i ra64num.inc}
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);
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regstabs_table : array[tregisterindex] of shortint = (
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{$i ra64sta.inc}
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);
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regdwarf_table : array[tregisterindex] of shortint = (
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{$i ra64dwa.inc}
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);
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{ registers which may be destroyed by calls }
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VOLATILE_INTREGISTERS = [RS_X0..RS_X18,RS_X29..RS_X30];
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VOLATILE_MMREGISTERS = [RS_D0..RS_D7,RS_D16..RS_D31];
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type
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totherregisterset = set of tregisterindex;
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{*****************************************************************************
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Instruction post fixes
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*****************************************************************************}
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type
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{ ARM instructions load/store and arithmetic instructions
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can have several instruction post fixes which are collected
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in this enumeration
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}
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TOpPostfix = (PF_None,
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{ update condition flags }
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PF_S,
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{ load/store }
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PF_B,PF_SB,PF_H,PF_SH
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);
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TOpPostfixes = set of TOpPostfix;
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const
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oppostfix2str : array[TOpPostfix] of string[2] = ('',
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's',
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'b','sb','h','sh');
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{*****************************************************************************
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Conditions
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*****************************************************************************}
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type
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TAsmCond=(C_None,
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C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
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C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
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);
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TAsmConds = set of TAsmCond;
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const
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cond2str : array[TAsmCond] of string[2]=('',
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'eq','ne','cs','cc','mi','pl','vs','vc','hi','ls',
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'ge','lt','gt','le','al','nv'
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);
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uppercond2str : array[TAsmCond] of string[2]=('',
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'EQ','NE','CS','CC','MI','PL','VS','VC','HI','LS',
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'GE','LT','GT','LE','AL','NV'
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);
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{*****************************************************************************
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Flags
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*****************************************************************************}
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type
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TResFlags = (F_EQ,F_NE,F_CS,F_CC,F_MI,F_PL,F_VS,F_VC,F_HI,F_LS,
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F_GE,F_LT,F_GT,F_LE);
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{*****************************************************************************
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Operands
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*****************************************************************************}
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taddressmode = (AM_OFFSET,AM_PREINDEXED,AM_POSTINDEXED);
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tshiftmode = (SM_None,SM_LSL,SM_LSR,SM_ASR,SM_ROR,SM_RRX);
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tupdatereg = (UR_None,UR_Update);
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pshifterop = ^tshifterop;
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tshifterop = record
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shiftmode : tshiftmode;
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rs : tregister;
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shiftimm : byte;
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end;
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tcpumodeflag = (mfA, mfI, mfF);
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tcpumodeflags = set of tcpumodeflag;
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tspecialregflag = (srC, srX, srS, srF);
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tspecialregflags = set of tspecialregflag;
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{*****************************************************************************
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Constants
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*****************************************************************************}
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const
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max_operands = 6;
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maxintregs = 15;
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maxfpuregs = 8;
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maxaddrregs = 0;
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{*****************************************************************************
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Operand Sizes
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*****************************************************************************}
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type
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topsize = (S_NO,
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S_B,S_W,S_L,S_BW,S_BL,S_WL,
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S_IS,S_IL,S_IQ,
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S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
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);
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{*****************************************************************************
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Default generic sizes
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*****************************************************************************}
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const
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{ Defines the default address size for a processor, }
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OS_ADDR = OS_64;
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{ the natural int size for a processor,
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has to match osuinttype/ossinttype as initialized in psystem }
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OS_INT = OS_64;
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OS_SINT = OS_S64;
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{ the maximum float size for a processor, }
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OS_FLOAT = OS_F64;
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{ the size of a vector register for a processor }
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OS_VECTOR = OS_M128;
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{*****************************************************************************
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Generic Register names
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*****************************************************************************}
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NR_SP = NR_XZR;
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RS_SP = RS_XZR;
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NR_WSP = NR_WZR;
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RS_WSP = RS_WZR;
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{ Stack pointer register }
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NR_STACK_POINTER_REG = NR_SP;
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RS_STACK_POINTER_REG = RS_SP;
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{ Frame pointer register (initialized in tarmprocinfo.init_framepointer) }
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RS_FRAME_POINTER_REG: tsuperregister = RS_X29;
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NR_FRAME_POINTER_REG: tregister = NR_X29;
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{ Register for addressing absolute data in a position independant way,
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such as in PIC code. The exact meaning is ABI specific. For
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further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
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}
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NR_PIC_OFFSET_REG = NR_X18;
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{ Results are returned in this register (32-bit values) }
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NR_FUNCTION_RETURN_REG = NR_X0;
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RS_FUNCTION_RETURN_REG = RS_X0;
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{ The value returned from a function is available in this register }
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NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
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RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
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NR_FPU_RESULT_REG = NR_NO;
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NR_MM_RESULT_REG = NR_D0;
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NR_RETURN_ADDRESS_REG = NR_FUNCTION_RETURN_REG;
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{ Offset where the parent framepointer is pushed }
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PARENT_FRAMEPOINTER_OFFSET = 0;
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NR_DEFAULTFLAGS = NR_NZCV;
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RS_DEFAULTFLAGS = RS_NZCV;
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{*****************************************************************************
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GCC /ABI linking information
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*****************************************************************************}
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const
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{ Registers which must be saved when calling a routine declared as
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cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
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saved should be the ones as defined in the target ABI and / or GCC.
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This value can be deduced from the CALLED_USED_REGISTERS array in the
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GCC source.
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}
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saved_standard_registers : array[0..9] of tsuperregister =
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(RS_X19,RS_X20,RS_X21,RS_X22,RS_X23,RS_X24,RS_X25,RS_X26,RS_X27,RS_X28);
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{ this is only for the generic code which is not used for this architecture }
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saved_mm_registers : array[0..7] of tsuperregister = (RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15);
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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{ Returns the tcgsize corresponding with the size of reg.}
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function reg_cgsize(const reg: tregister) : tcgsize;
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function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
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function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
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procedure inverse_flags(var f: TResFlags);
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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function findreg_by_number(r:Tregister):tregisterindex;
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function std_regnum_search(const s:string):Tregister;
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function std_regname(r:Tregister):string;
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function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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procedure shifterop_reset(var so : tshifterop); {$ifdef USEINLINE}inline;{$endif USEINLINE}
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function dwarf_reg(r:tregister):shortint;
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implementation
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uses
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systems,rgBase,verbose;
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const
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std_regname_table : TRegNameTable = (
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{$i ra64std.inc}
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);
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regnumber_index : array[tregisterindex] of tregisterindex = (
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{$i ra64rni.inc}
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);
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std_regname_index : array[tregisterindex] of tregisterindex = (
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{$i ra64sri.inc}
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);
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function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
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begin
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case regtype of
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R_MMREGISTER:
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begin
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case s of
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OS_F32:
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cgsize2subreg:=R_SUBFS;
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OS_F64:
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cgsize2subreg:=R_SUBFD;
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else
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internalerror(2009112701);
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end;
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end;
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else
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cgsize2subreg:=R_SUBWHOLE;
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end;
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end;
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function reg_cgsize(const reg: tregister): tcgsize;
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begin
|
|
|
|
|
case getregtype(reg) of
|
|
|
|
|
R_INTREGISTER :
|
|
|
|
|
reg_cgsize:=OS_32;
|
|
|
|
|
R_FPUREGISTER :
|
|
|
|
|
reg_cgsize:=OS_F80;
|
|
|
|
|
R_MMREGISTER :
|
|
|
|
|
begin
|
|
|
|
|
case getsubreg(reg) of
|
|
|
|
|
R_SUBFD,
|
|
|
|
|
R_SUBWHOLE:
|
|
|
|
|
result:=OS_F64;
|
|
|
|
|
R_SUBFS:
|
|
|
|
|
result:=OS_F32;
|
|
|
|
|
else
|
|
|
|
|
internalerror(2009112903);
|
|
|
|
|
end;
|
|
|
|
|
end;
|
|
|
|
|
else
|
|
|
|
|
internalerror(200303181);
|
|
|
|
|
end;
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
|
|
|
|
|
begin
|
|
|
|
|
{ This isn't 100% perfect because the arm allows jumps also by writing to PC=R15.
|
|
|
|
|
To overcome this problem we simply forbid that FPC generates jumps by loading R15 }
|
|
|
|
|
is_calljmp:= o in [A_B,A_BLR,A_RET];
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
procedure inverse_flags(var f: TResFlags);
|
|
|
|
|
const
|
|
|
|
|
inv_flags: array[TResFlags] of TResFlags =
|
|
|
|
|
(F_NE,F_EQ,F_CC,F_CS,F_PL,F_MI,F_VC,F_VS,F_LS,F_HI,
|
|
|
|
|
F_LT,F_GE,F_LE,F_GT);
|
|
|
|
|
begin
|
|
|
|
|
f:=inv_flags[f];
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function flags_to_cond(const f: TResFlags) : TAsmCond;
|
|
|
|
|
const
|
|
|
|
|
flag_2_cond: array[F_EQ..F_LE] of TAsmCond =
|
|
|
|
|
(C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
|
|
|
|
|
C_GE,C_LT,C_GT,C_LE);
|
|
|
|
|
begin
|
|
|
|
|
if f>high(flag_2_cond) then
|
|
|
|
|
internalerror(200112301);
|
|
|
|
|
result:=flag_2_cond[f];
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function findreg_by_number(r:Tregister):tregisterindex;
|
|
|
|
|
begin
|
|
|
|
|
result:=rgBase.findreg_by_number_table(r,regnumber_index);
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function std_regnum_search(const s:string):Tregister;
|
|
|
|
|
begin
|
|
|
|
|
result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function std_regname(r:Tregister):string;
|
|
|
|
|
var
|
|
|
|
|
p : tregisterindex;
|
|
|
|
|
begin
|
|
|
|
|
p:=findreg_by_number_table(r,regnumber_index);
|
|
|
|
|
if p<>0 then
|
|
|
|
|
result:=std_regname_table[p]
|
|
|
|
|
else
|
|
|
|
|
result:=generic_regname(r);
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
procedure shifterop_reset(var so : tshifterop);{$ifdef USEINLINE}inline;{$endif USEINLINE}
|
|
|
|
|
begin
|
|
|
|
|
FillChar(so,sizeof(so),0);
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
|
|
|
|
|
const
|
|
|
|
|
inverse: array[TAsmCond] of TAsmCond=(C_None,
|
|
|
|
|
C_NE,C_EQ,C_CC,C_CS,C_PL,C_MI,C_VC,C_VS,C_LS,C_HI,
|
|
|
|
|
C_LT,C_GE,C_LE,C_GT,C_None,C_None
|
|
|
|
|
);
|
|
|
|
|
begin
|
|
|
|
|
result := inverse[c];
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
|
|
|
|
|
begin
|
|
|
|
|
result := c1 = c2;
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
function dwarf_reg(r:tregister):shortint;
|
|
|
|
|
begin
|
|
|
|
|
result:=regdwarf_table[findreg_by_number(r)];
|
|
|
|
|
if result=-1 then
|
|
|
|
|
internalerror(200603251);
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
end.
|
florian