+ RiscV: handle rol(w) in the assembler optimizer

2025-04-05 01:01:33 +02:00 · 2025-03-23 23:04:17 +01:00 · 2025-03-23 23:04:17 +01:00 · cafaa9f5b8
commit cafaa9f5b8
parent 0d5dddfcb5
1 changed files with 2 additions and 0 deletions
--- a/compiler/riscv/aoptcpurv.pas
+++ b/compiler/riscv/aoptcpurv.pas
@ -916,10 +916,12 @@ implementation
              A_SLLW,
              A_SRLW,
              A_SRAW,
+              A_ROLW,
 {$endif riscv64}
              A_SLL,
              A_SRL,
              A_SRA,
+              A_ROL,
              A_NEG,
              A_NOT:
                result:=OptPass1OP(p);