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* check for eax,edx,ecx,ebx that support 8,16 bit registers in shortint add/sub peephole
and update register size of substructor git-svn-id: trunk@9351 -
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@ -1265,6 +1265,7 @@ begin
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GetNextInstruction(p,hp1) and
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(hp1.typ = ait_instruction) and
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IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX]) and
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GetNextInstruction(hp1,hp2) and
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(hp2.typ = ait_instruction) and
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(taicpu(hp2).opcode = A_MOV) and
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@ -1275,8 +1276,10 @@ begin
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{ mov reg2 reg/ref }
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{ to add/sub/or/... reg3/$const, reg/ref }
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begin
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taicpu(hp1).opsize:=taicpu(hp2).opsize;
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taicpu(hp1).changeopsize(taicpu(hp2).opsize);
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taicpu(hp1).loadoper(1,taicpu(hp2).oper[1]^);
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if (taicpu(hp1).oper[0]^.typ = top_reg) then
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setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
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asml.remove(p);
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asml.remove(hp2);
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p.free;
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