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* Further work to convert codegenerator register convention;

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internalerror bug fixed.
This commit is contained in:
daniel 2003-01-13 14:54:34 +00:00
parent c134e2d478
commit cbe0383afe
7 changed files with 160 additions and 67 deletions
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10
compiler/cgobj.pas
View File

@ -777,6 +777,10 @@ unit cgobj;
procedure tcg.a_load_loc_reg(list : taasmoutput;const loc: tlocation; reg : tregister); procedure tcg.a_load_loc_reg(list : taasmoutput;const loc: tlocation; reg : tregister);
begin begin
{$ifdef i386}
{For safety convert location register to enum for now...}
convert_register_to_enum(reg);
{$endif}
case loc.loc of case loc.loc of
LOC_REFERENCE,LOC_CREFERENCE: LOC_REFERENCE,LOC_CREFERENCE:
a_load_ref_reg(list,loc.size,loc.reference,reg); a_load_ref_reg(list,loc.size,loc.reference,reg);
@ -1694,7 +1698,11 @@ finalization
end. end.
{ {
$Log$ $Log$
Revision 1.72 2003-01-09 22:00:53 florian Revision 1.73 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.72 2003/01/09 22:00:53 florian
* fixed some PowerPC issues * fixed some PowerPC issues
Revision 1.71 2003/01/09 20:41:10 florian Revision 1.71 2003/01/09 20:41:10 florian

8
compiler/i386/cga.pas
View File

@ -152,6 +152,8 @@ implementation
procedure emit_reg_reg(i : tasmop;s : topsize;reg1,reg2 : tregister); procedure emit_reg_reg(i : tasmop;s : topsize;reg1,reg2 : tregister);
begin begin
convert_register_to_enum(reg1);
convert_register_to_enum(reg2);
if (reg1.enum<>reg2.enum) or (i<>A_MOV) then if (reg1.enum<>reg2.enum) or (i<>A_MOV) then
exprasmList.concat(Taicpu.Op_reg_reg(i,s,reg1,reg2)); exprasmList.concat(Taicpu.Op_reg_reg(i,s,reg1,reg2));
end; end;
@ -174,7 +176,11 @@ implementation
end. end.
{ {
$Log$ $Log$
Revision 1.34 2003-01-08 18:43:57 daniel Revision 1.35 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.34 2003/01/08 18:43:57 daniel
* Tregister changed into a record * Tregister changed into a record
Revision 1.33 2002/07/01 18:46:29 peter Revision 1.33 2002/07/01 18:46:29 peter

35
compiler/i386/n386mat.pas
View File

@ -121,7 +121,8 @@ implementation
else else
begin begin
rg.getexplicitregisterint(exprasmlist,R_EDI); rg.getexplicitregisterint(exprasmlist,R_EDI);
hreg2.enum := R_EDI; hreg2.enum := R_INTREGISTER;
hreg2.number := NR_EDI;
emit_reg_reg(A_MOV,S_L,hreg1,hreg2); emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
{ if the left value is signed, R_EDI := $ffffffff, { if the left value is signed, R_EDI := $ffffffff,
otherwise 0 } otherwise 0 }
@ -133,6 +134,8 @@ implementation
emit_reg_reg(A_ADD,S_L,hreg2,hreg1); emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
{ release EDX if we used it } { release EDX if we used it }
{ also releas EDI } { also releas EDI }
if (hreg2.enum=R_INTREGISTER) and (hreg2.number=NR_EDI) then
hreg2.enum:=R_EDI;
rg.ungetregisterint(exprasmlist,hreg2); rg.ungetregisterint(exprasmlist,hreg2);
{ do the shift } { do the shift }
emit_const_reg(A_SAR,S_L,power,hreg1); emit_const_reg(A_SAR,S_L,power,hreg1);
@ -163,12 +166,14 @@ implementation
rg.getexplicitregisterint(exprasmlist,R_EDI); rg.getexplicitregisterint(exprasmlist,R_EDI);
if right.location.loc<>LOC_CREGISTER then if right.location.loc<>LOC_CREGISTER then
location_release(exprasmlist,right.location); location_release(exprasmlist,right.location);
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
cg.a_load_loc_reg(exprasmlist,right.location,r); cg.a_load_loc_reg(exprasmlist,right.location,r);
popedx:=false; popedx:=false;
popeax:=false; popeax:=false;
r.enum:=R_EAX; r.number:=NR_EAX;
r2.enum:=R_EDX; r2.enum:=R_INTREGISTER;
r2.number:=NR_EDX;
if hreg1.enum=R_EDX then if hreg1.enum=R_EDX then
begin begin
if not(R_EAX in rg.unusedregsint) then if not(R_EAX in rg.unusedregsint) then
@ -208,18 +213,23 @@ implementation
emit_none(A_CDQ,S_NO); emit_none(A_CDQ,S_NO);
{ division depends on the right type } { division depends on the right type }
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
if torddef(right.resulttype.def).typ=u32bit then if torddef(right.resulttype.def).typ=u32bit then
emit_reg(A_DIV,S_L,r) emit_reg(A_DIV,S_L,r)
else else
emit_reg(A_IDIV,S_L,r); emit_reg(A_IDIV,S_L,r);
r.enum:=R_EDI; r.enum:=R_EDI;
rg.ungetregisterint(exprasmlist,r); rg.ungetregisterint(exprasmlist,r);
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
if nodetype=divn then if nodetype=divn then
begin begin
if not popedx and (hreg1.enum <> R_EDX) then if not popedx and (hreg1.enum <> R_EDX) then
rg.ungetregister(exprasmlist,r2); begin
r2.enum:=R_EDX;
rg.ungetregister(exprasmlist,r2);
end;
{ if result register is busy then copy } { if result register is busy then copy }
if popeax then if popeax then
begin begin
@ -239,7 +249,10 @@ implementation
else else
begin begin
if not popeax and (hreg1.enum <> R_EAX)then if not popeax and (hreg1.enum <> R_EAX)then
rg.ungetregister(exprasmlist,r); begin
r.enum:=R_EAX;
rg.ungetregister(exprasmlist,r);
end;
if popedx then if popedx then
{the mod was done by an (i)div (so the result is now in {the mod was done by an (i)div (so the result is now in
edx), but edx was occupied prior to the division, so edx), but edx was occupied prior to the division, so
@ -862,7 +875,11 @@ begin
end. end.
{ {
$Log$ $Log$
Revision 1.42 2003-01-08 18:43:57 daniel Revision 1.43 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.42 2003/01/08 18:43:57 daniel
* Tregister changed into a record * Tregister changed into a record
Revision 1.41 2002/11/25 17:43:26 peter Revision 1.41 2002/11/25 17:43:26 peter

29
compiler/i386/n386obj.pas
View File

@ -113,9 +113,10 @@ procedure ti386classheader.cgintfwrapper(asmlist: TAAsmoutput; procdef: tprocdef
r:Tregister; r:Tregister;
begin begin
{ mov offset(%esp),%eax } { mov offset(%esp),%eax }
r.enum:=R_ESP; r.enum:=R_INTREGISTER;
r.number:=NR_ESP;
reference_reset_base(href,r,getselfoffsetfromsp(procdef)); reference_reset_base(href,r,getselfoffsetfromsp(procdef));
r.enum:=R_EAX; r.number:=NR_EAX;
cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,r); cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,r);
end; end;
@ -126,7 +127,8 @@ procedure ti386classheader.cgintfwrapper(asmlist: TAAsmoutput; procdef: tprocdef
begin begin
checkvirtual; checkvirtual;
{ mov 0(%eax),%eax ; load vmt} { mov 0(%eax),%eax ; load vmt}
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
reference_reset_base(href,r,0); reference_reset_base(href,r,0);
emit_ref_reg(A_MOV,S_L,href,r); emit_ref_reg(A_MOV,S_L,href,r);
end; end;
@ -137,7 +139,8 @@ procedure ti386classheader.cgintfwrapper(asmlist: TAAsmoutput; procdef: tprocdef
r:Tregister; r:Tregister;
begin begin
{ call/jmp vmtoffs(%eax) ; method offs } { call/jmp vmtoffs(%eax) ; method offs }
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
reference_reset_base(href,r,procdef._class.vmtmethodoffset(procdef.extnumber)); reference_reset_base(href,r,procdef._class.vmtmethodoffset(procdef.extnumber));
emit_ref(op,S_L,href); emit_ref(op,S_L,href);
end; end;
@ -148,7 +151,8 @@ procedure ti386classheader.cgintfwrapper(asmlist: TAAsmoutput; procdef: tprocdef
r:Tregister; r:Tregister;
begin begin
{ mov vmtoffs(%eax),%eax ; method offs } { mov vmtoffs(%eax),%eax ; method offs }
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
reference_reset_base(href,r,procdef._class.vmtmethodoffset(procdef.extnumber)); reference_reset_base(href,r,procdef._class.vmtmethodoffset(procdef.extnumber));
emit_ref_reg(A_MOV,S_L,href,r); emit_ref_reg(A_MOV,S_L,href,r);
end; end;
@ -203,17 +207,18 @@ begin
{ case 3 } { case 3 }
else if [po_virtualmethod,po_saveregisters]*procdef.procoptions=[po_virtualmethod,po_saveregisters] then else if [po_virtualmethod,po_saveregisters]*procdef.procoptions=[po_virtualmethod,po_saveregisters] then
begin begin
r.enum:=R_EBX; r.enum:=R_INTREGISTER;
r.number:=NR_EBX;
emit_reg(A_PUSH,S_L,r); { allocate space for address} emit_reg(A_PUSH,S_L,r); { allocate space for address}
r.enum:=R_EAX; r.number:=NR_EAX;
emit_reg(A_PUSH,S_L,r); emit_reg(A_PUSH,S_L,r);
getselftoeax(8); getselftoeax(8);
loadvmttoeax; loadvmttoeax;
loadmethodoffstoeax; loadmethodoffstoeax;
{ mov %eax,4(%esp) } { mov %eax,4(%esp) }
r.enum:=R_ESP; r.number:=NR_ESP;
reference_reset_base(href,r,4); reference_reset_base(href,r,4);
r.enum:=R_EAX; r.number:=NR_EAX;
emit_reg_ref(A_MOV,S_L,r,href); emit_reg_ref(A_MOV,S_L,r,href);
{ pop %eax } { pop %eax }
emit_reg(A_POP,S_L,r); emit_reg(A_POP,S_L,r);
@ -242,7 +247,11 @@ initialization
end. end.
{ {
$Log$ $Log$
Revision 1.16 2003-01-08 18:43:57 daniel Revision 1.17 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.16 2003/01/08 18:43:57 daniel
* Tregister changed into a record * Tregister changed into a record
Revision 1.15 2002/08/11 14:32:30 peter Revision 1.15 2002/08/11 14:32:30 peter

14
compiler/i386/n386set.pas
View File

@ -279,7 +279,8 @@ implementation
if (pleftreg.enum <> R_EDI) and if (pleftreg.enum <> R_EDI) and
(left.location.loc = LOC_CREGISTER) then (left.location.loc = LOC_CREGISTER) then
begin begin
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
rg.ungetregister(exprasmlist,pleftreg); rg.ungetregister(exprasmlist,pleftreg);
rg.getexplicitregisterint(exprasmlist,R_EDI); rg.getexplicitregisterint(exprasmlist,R_EDI);
reference_reset_base(href,pleftreg,-setparts[i].start); reference_reset_base(href,pleftreg,-setparts[i].start);
@ -397,7 +398,8 @@ implementation
{ the set element isn't never samller than a byte } { the set element isn't never samller than a byte }
{ and because it's a small set we need only 5 bits } { and because it's a small set we need only 5 bits }
{ but 8 bits are easier to load } { but 8 bits are easier to load }
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
rg.getexplicitregisterint(exprasmlist,R_EDI); rg.getexplicitregisterint(exprasmlist,R_EDI);
emit_ref_reg(A_MOVZX,S_BL,left.location.reference,r); emit_ref_reg(A_MOVZX,S_BL,left.location.reference,r);
hr:=r; hr:=r;
@ -433,6 +435,8 @@ implementation
internalerror(2002032210); internalerror(2002032210);
end; end;
{ simply to indicate EDI is deallocated here too (JM) } { simply to indicate EDI is deallocated here too (JM) }
if (hr.enum=R_INTREGISTER) and (hr.number=NR_EDI) then
hr.enum:=R_EDI;
rg.ungetregisterint(exprasmlist,hr); rg.ungetregisterint(exprasmlist,hr);
location.loc:=LOC_FLAGS; location.loc:=LOC_FLAGS;
location.resflags:=F_C; location.resflags:=F_C;
@ -710,7 +714,11 @@ begin
end. end.
{ {
$Log$ $Log$
Revision 1.46 2003-01-08 18:43:57 daniel Revision 1.47 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.46 2003/01/08 18:43:57 daniel
* Tregister changed into a record * Tregister changed into a record
Revision 1.45 2002/11/25 17:43:27 peter Revision 1.45 2002/11/25 17:43:27 peter

7
compiler/nobj.pas
View File

@ -1011,6 +1011,7 @@ implementation
end; end;
dataSegment.concatlist(rawdata); dataSegment.concatlist(rawdata);
rawdata.free; rawdata.free;
rawcode.convert_registers;
codeSegment.concatlist(rawcode); codeSegment.concatlist(rawcode);
rawcode.free; rawcode.free;
freemem(impintfindexes,(max+1)*sizeof(longint)); freemem(impintfindexes,(max+1)*sizeof(longint));
@ -1332,7 +1333,11 @@ initialization
end. end.
{ {
$Log$ $Log$
Revision 1.39 2003-01-09 21:52:37 peter Revision 1.40 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.39 2003/01/09 21:52:37 peter
* merged some verbosity options. * merged some verbosity options.
* V_LineInfo is a verbosity flag to include line info * V_LineInfo is a verbosity flag to include line info

124
compiler/x86/cgx86.pas
View File

@ -480,10 +480,22 @@ unit cgx86;
var var
op: tasmop; op: tasmop;
s: topsize; s: topsize;
eq:boolean;
begin begin
sizes2load(fromsize,reg2opsize[reg2.enum],op,s); if (reg1.enum=R_INTREGISTER) and (reg2.enum=R_INTREGISTER) then
if (rg.makeregsize(reg1,OS_INT).enum = rg.makeregsize(reg2,OS_INT).enum) then begin
sizes2load(fromsize,subreg2opsize[reg2.number and $ff],op,s);
eq:=(reg1.number shr 8)=(reg2.number shr 8);
end
else if (reg1.enum<lastreg) and (reg2.enum<lastreg) then
begin
sizes2load(fromsize,reg2opsize[reg2.enum],op,s);
eq:=(rg.makeregsize(reg1,OS_INT).enum = rg.makeregsize(reg2,OS_INT).enum);
end
else
internalerror(200301081);
if eq then
begin begin
{ "mov reg1, reg1" doesn't make sense } { "mov reg1, reg1" doesn't make sense }
if op = A_MOV then if op = A_MOV then
@ -787,6 +799,7 @@ unit cgx86;
internalerror(200301081); internalerror(200301081);
if dst.enum>lastreg then if dst.enum>lastreg then
internalerror(200301081); internalerror(200301081);
r.enum:=R_INTREGISTER;
dstsize := tcgsize2opsize[size]; dstsize := tcgsize2opsize[size];
dst := rg.makeregsize(dst,size); dst := rg.makeregsize(dst,size);
case op of case op of
@ -820,23 +833,22 @@ unit cgx86;
begin begin
{ is ecx still free (it's also free if it was allocated } { is ecx still free (it's also free if it was allocated }
{ to dst, since we've moved dst somewhere else already) } { to dst, since we've moved dst somewhere else already) }
r.number:=NR_ECX;
if not((dst.enum = R_ECX) or if not((dst.enum = R_ECX) or
((R_ECX in rg.unusedregsint) and ((R_ECX in rg.unusedregsint) and
{ this will always be true, it's just here to } { this will always be true, it's just here to }
{ allocate ecx } { allocate ecx }
(rg.getexplicitregisterint(list,R_ECX).enum = R_ECX))) then (rg.getexplicitregisterint(list,R_ECX).enum = R_ECX))) then
begin begin
r.enum:=R_ECX;
list.concat(taicpu.op_reg(A_PUSH,S_L,r)); list.concat(taicpu.op_reg(A_PUSH,S_L,r));
popecx := true; popecx := true;
end; end;
r.enum:=R_ECX;
a_load_reg_reg(list,OS_32,OS_32,rg.makeregsize(src,OS_32),r); a_load_reg_reg(list,OS_32,OS_32,rg.makeregsize(src,OS_32),r);
end end
else else
src.enum := R_CL; src.enum := R_CL;
{ do the shift } { do the shift }
r.enum:=R_CL; r.number:=NR_CL;
if tmpreg.enum = R_NO then if tmpreg.enum = R_NO then
list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dstsize, list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dstsize,
r,dst)) r,dst))
@ -845,11 +857,11 @@ unit cgx86;
list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],S_L, list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],S_L,
r,tmpreg)); r,tmpreg));
{ move result back to the destination } { move result back to the destination }
r.enum:=R_ECX; r.number:=NR_ECX;
a_load_reg_reg(list,OS_32,OS_32,tmpreg,r); a_load_reg_reg(list,OS_32,OS_32,tmpreg,r);
free_scratch_reg(list,tmpreg); free_scratch_reg(list,tmpreg);
end; end;
r.enum:=R_ECX; r.number:=NR_ECX;
if popecx then if popecx then
list.concat(taicpu.op_reg(A_POP,S_L,r)) list.concat(taicpu.op_reg(A_POP,S_L,r))
else if not (dst.enum in [R_ECX,R_CX,R_CL]) then else if not (dst.enum in [R_ECX,R_CX,R_CL]) then
@ -1133,7 +1145,8 @@ unit cgx86;
var r:Tregister; var r:Tregister;
begin begin
r.enum:=R_ECX; r.enum:=R_INTREGISTER;
r.number:=NR_ECX;
if not(R_ECX in rg.unusedregsint) then if not(R_ECX in rg.unusedregsint) then
begin begin
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
@ -1147,13 +1160,14 @@ unit cgx86;
((len<=8) or ((len<=8) or
(not(cs_littlesize in aktglobalswitches ) and (len<=12))) then (not(cs_littlesize in aktglobalswitches ) and (len<=12))) then
begin begin
r.enum:=R_INTREGISTER;
helpsize:=len shr 2; helpsize:=len shr 2;
rg.getexplicitregisterint(list,R_EDI); rg.getexplicitregisterint(list,R_EDI);
dstref:=dest; dstref:=dest;
srcref:=source; srcref:=source;
for i:=1 to helpsize do for i:=1 to helpsize do
begin begin
r.enum:=R_EDI; r.number:=NR_EDI;
a_load_ref_reg(list,OS_32,srcref,r); a_load_ref_reg(list,OS_32,srcref,r);
If (len = 4) and delsource then If (len = 4) and delsource then
reference_release(list,source); reference_release(list,source);
@ -1164,7 +1178,7 @@ unit cgx86;
end; end;
if len>1 then if len>1 then
begin begin
r.enum:=R_DI; r.number:=NR_DI;
a_load_ref_reg(list,OS_16,srcref,r); a_load_ref_reg(list,OS_16,srcref,r);
If (len = 2) and delsource then If (len = 2) and delsource then
reference_release(list,source); reference_release(list,source);
@ -1175,6 +1189,9 @@ unit cgx86;
end; end;
r.enum:=R_EDI; r.enum:=R_EDI;
rg.ungetregisterint(list,r); rg.ungetregisterint(list,r);
r.enum:=R_INTREGISTER;
reg8.enum:=R_INTREGISTER;
reg32.enum:=R_INTREGISTER;
if len>0 then if len>0 then
begin begin
{ and now look for an 8 bit register } { and now look for an 8 bit register }
@ -1190,25 +1207,25 @@ unit cgx86;
{ one is always not index or base } { one is always not index or base }
if (dest.base.enum<>R_EAX) and (dest.index.enum<>R_EAX) then if (dest.base.enum<>R_EAX) and (dest.index.enum<>R_EAX) then
begin begin
reg8.enum:=R_AL; reg8.number:=NR_AL;
reg32.enum:=R_EAX; reg32.number:=NR_EAX;
end end
else if (dest.base.enum<>R_EBX) and (dest.index.enum<>R_EBX) then else if (dest.base.enum<>R_EBX) and (dest.index.enum<>R_EBX) then
begin begin
reg8.enum:=R_BL; reg8.number:=NR_BL;
reg32.enum:=R_EBX; reg32.number:=NR_EBX;
end end
else if (dest.base.enum<>R_ECX) and (dest.index.enum<>R_ECX) then else if (dest.base.enum<>R_ECX) and (dest.index.enum<>R_ECX) then
begin begin
reg8.enum:=R_CL; reg8.number:=NR_CL;
reg32.enum:=R_ECX; reg32.number:=NR_ECX;
end; end;
end; end;
if swap then if swap then
{ was earlier XCHG, of course nonsense } { was earlier XCHG, of course nonsense }
begin begin
rg.getexplicitregisterint(list,R_EDI); rg.getexplicitregisterint(list,R_EDI);
r.enum:=R_EDI; r.number:=NR_EDI;
a_load_reg_reg(list,OS_32,OS_32,reg32,r); a_load_reg_reg(list,OS_32,OS_32,reg32,r);
end; end;
a_load_ref_reg(list,OS_8,srcref,reg8); a_load_ref_reg(list,OS_8,srcref,reg8);
@ -1217,21 +1234,31 @@ unit cgx86;
a_load_reg_ref(list,OS_8,reg8,dstref); a_load_reg_ref(list,OS_8,reg8,dstref);
if swap then if swap then
begin begin
r.enum:=R_EDI; r.number:=NR_EDI;
a_load_reg_reg(list,OS_32,OS_32,r,reg32); a_load_reg_reg(list,OS_32,OS_32,r,reg32);
r.enum:=R_EDI;
rg.ungetregisterint(list,r); rg.ungetregisterint(list,r);
end end
else else
rg.ungetregister(list,reg8); begin
if reg8.number=NR_AL then
reg8.enum:=R_AL
else if reg8.number=NR_BL then
reg8.enum:=R_BL
else if reg8.number=NR_CL then
reg8.enum:=R_CL;
rg.ungetregister(list,reg8);
end;
end; end;
end end
else else
begin begin
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
rg.getexplicitregisterint(list,R_EDI); rg.getexplicitregisterint(list,R_EDI);
a_loadaddr_ref_reg(list,dest,r); a_loadaddr_ref_reg(list,dest,r);
r.enum:=R_ESI; r.number:=NR_ESI;
list.concat(tai_regalloc.Alloc(r)); list.concat(tai_regalloc.alloc(r));
if loadref then if loadref then
a_load_ref_reg(list,OS_ADDR,source,r) a_load_ref_reg(list,OS_ADDR,source,r)
else else
@ -1243,7 +1270,7 @@ unit cgx86;
list.concat(Taicpu.Op_none(A_CLD,S_NO)); list.concat(Taicpu.Op_none(A_CLD,S_NO));
ecxpushed:=false; ecxpushed:=false;
r.enum:=R_ECX; r.number:=NR_ECX;
if cs_littlesize in aktglobalswitches then if cs_littlesize in aktglobalswitches then
begin begin
maybepushecx; maybepushecx;
@ -1273,13 +1300,19 @@ unit cgx86;
end; end;
r.enum:=R_EDI; r.enum:=R_EDI;
rg.ungetregisterint(list,r); rg.ungetregisterint(list,r);
r.enum:=R_ESI; r.enum:=R_INTREGISTER;
list.concat(tai_regalloc.DeAlloc(r)); r.number:=NR_ESI;
r.enum:=R_ECX; list.concat(tai_regalloc.dealloc(r));
if ecxpushed then if ecxpushed then
list.concat(Taicpu.Op_reg(A_POP,S_L,r)) begin
r.number:=NR_ECX;
list.concat(Taicpu.Op_reg(A_POP,S_L,r))
end
else else
rg.ungetregisterint(list,r); begin
r.enum:=R_ECX;
rg.ungetregisterint(list,r);
end;
{ loading SELF-reference again } { loading SELF-reference again }
g_maybe_loadself(list); g_maybe_loadself(list);
@ -1295,7 +1328,8 @@ unit cgx86;
var r:Tregister; var r:Tregister;
begin begin
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
list.concat(Taicpu.op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.op_reg(A_PUSH,S_L,r));
end; end;
@ -1310,7 +1344,8 @@ unit cgx86;
var r:Tregister; var r:Tregister;
begin begin
r.enum:=R_EAX; r.enum:=R_INTREGISTER;
r.number:=NR_EAX;
list.concat(Taicpu.op_reg(A_POP,S_L,r)); list.concat(Taicpu.op_reg(A_POP,S_L,r));
end; end;
@ -1469,27 +1504,27 @@ unit cgx86;
begin begin
r.enum:=R_INTREGISTER; r.enum:=R_INTREGISTER;
r.enum:=R_GS; r.number:=NR_GS;
{ .... also the segment registers } { .... also the segment registers }
list.concat(Taicpu.Op_reg(A_PUSH,S_W,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
r.enum:=R_FS; r.number:=NR_FS;
list.concat(Taicpu.Op_reg(A_PUSH,S_W,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
r.enum:=R_ES; r.number:=NR_ES;
list.concat(Taicpu.Op_reg(A_PUSH,S_W,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
r.enum:=R_DS; r.number:=NR_DS;
list.concat(Taicpu.Op_reg(A_PUSH,S_W,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
{ save the registers of an interrupt procedure } { save the registers of an interrupt procedure }
r.enum:=R_EDI; r.number:=NR_EDI;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
r.enum:=R_ESI; r.number:=NR_ESI;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
r.enum:=R_EDX; r.number:=NR_EDX;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
r.enum:=R_ECX; r.number:=NR_ECX;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
r.enum:=R_EBX; r.number:=NR_EBX;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
r.enum:=R_EAX; r.number:=NR_EAX;
list.concat(Taicpu.Op_reg(A_PUSH,S_L,r)); list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
end; end;
@ -1687,7 +1722,8 @@ unit cgx86;
var r:Tregister; var r:Tregister;
begin begin
r.enum:=R_EDI; r.enum:=R_INTREGISTER;
r.number:=NR_EDI;
if is_class(procinfo._class) then if is_class(procinfo._class) then
begin begin
if (cs_implicit_exceptions in aktmoduleswitches) then if (cs_implicit_exceptions in aktmoduleswitches) then
@ -1874,7 +1910,11 @@ unit cgx86;
end. end.
{ {
$Log$ $Log$
Revision 1.28 2003-01-09 20:41:00 daniel Revision 1.29 2003-01-13 14:54:34 daniel
* Further work to convert codegenerator register convention;
internalerror bug fixed.
Revision 1.28 2003/01/09 20:41:00 daniel
* Converted some code in cgx86.pas to new register numbering * Converted some code in cgx86.pas to new register numbering
Revision 1.27 2003/01/08 18:43:58 daniel Revision 1.27 2003/01/08 18:43:58 daniel