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Fix comparisons (aka usage of flag/CCR register)

Browse Source 
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
  * add all Sxx instructions as "operand_write" instructions

m68k/n68kadd.pas, t68kaddnode.getresflags:
  * use the correct operation in case of swapped nodes

m68k/cgcpu.pas, tcg68k.g_flags2reg:
  - don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
  - NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
  * simplify the method by handling the address register case only when necessary

git-svn-id: trunk@23383 -
This commit is contained in:
svenbarth 2013-01-14 20:31:15 +00:00
parent 741992bae4
commit ccecf2c13c
3 changed files with 24 additions and 52 deletions
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3
compiler/m68k/aasmcpu.pas
View File

@ -528,7 +528,8 @@ type
end;
A_TST,A_CMP,A_CMPI:
result:=operand_read;
A_CLR, A_SXX:
A_CLR, A_SXX, A_SEQ, A_SNE, A_SLT, A_SLE, A_SGT, A_SGE, A_SCS, A_SCC,
A_SMI, A_SPL, A_SF, A_ST, A_SVS, A_SVC, A_SHI, A_SLS:
result:=operand_write;
A_NEG, A_EXT, A_EXTB, A_NOT, A_NEGX:
result:=operand_readwrite;

57
compiler/m68k/cgcpu.pas
View File

@ -1449,51 +1449,22 @@ unit cgcpu;
begin
{ move to a Dx register? }
if (isaddressregister(reg)) then
begin
hreg := getintregister(list,OS_INT);
a_load_const_reg(list,size,0,hreg);
ai:=Taicpu.Op_reg(A_Sxx,S_B,hreg);
ai.SetCondition(flags_to_cond(f));
list.concat(ai);
if (current_settings.cputype = cpu_ColdFire) then
begin
{ neg.b does not exist on the Coldfire
so we need to sign extend the value
before doing a neg.l
}
list.concat(taicpu.op_reg(A_EXTB,S_L,hreg));
list.concat(taicpu.op_reg(A_NEG,S_L,hreg));
end
else
begin
list.concat(taicpu.op_reg(A_NEG,S_B,hreg));
end;
instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg,reg);
add_move_instruction(instr);
list.concat(instr);
end
hreg:=getintregister(list,OS_INT)
else
begin
a_load_const_reg(list,size,0,reg);
ai:=Taicpu.Op_reg(A_Sxx,S_B,reg);
ai.SetCondition(flags_to_cond(f));
list.concat(ai);
hreg:=reg;
if (current_settings.cputype = cpu_ColdFire) then
begin
{ neg.b does not exist on the Coldfire
so we need to sign extend the value
before doing a neg.l
}
list.concat(taicpu.op_reg(A_EXTB,S_L,reg));
list.concat(taicpu.op_reg(A_NEG,S_L,reg));
end
else
begin
list.concat(taicpu.op_reg(A_NEG,S_B,reg));
end;
end;
ai:=Taicpu.Op_reg(A_Sxx,S_B,hreg);
ai.SetCondition(flags_to_cond(f));
list.concat(ai);
list.concat(taicpu.op_reg(A_EXTB,S_L,hreg));
if hreg<>reg then
begin
instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg,reg);
add_move_instruction(instr);
list.concat(instr);
end;
end;

16
compiler/m68k/n68kadd.pas
View File

@ -267,10 +267,10 @@ implementation
begin
if nf_swapped in flags then
case nodetype of
ltn : getresflags:=F_G;
lten : getresflags:=F_GE;
gtn : getresflags:=F_L;
gten : getresflags:=F_LE;
ltn : getresflags:=F_GE;
lten : getresflags:=F_G;
gtn : getresflags:=F_LE;
gten : getresflags:=F_L;
end
else
case nodetype of
@ -284,10 +284,10 @@ implementation
begin
if nf_swapped in flags then
case nodetype of
ltn : getresflags:=F_A;
lten : getresflags:=F_AE;
gtn : getresflags:=F_B;
gten : getresflags:=F_BE;
ltn : getresflags:=F_AE;
lten : getresflags:=F_A;
gtn : getresflags:=F_BE;
gten : getresflags:=F_B;
end
else
case nodetype of