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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-13 04:09:33 +02:00
+ enabled postpeepholeopts phase
+ optimize "integer op" followed by comparison of target register with zero
to a variant of that integer op which sets the flags (ppc)
+ change rlwinm. instructions which do nothing but an "and" operation into
andi./andis., since the rlwinm. is cracked on the G5 while andi./andis.
isn't
git-svn-id: trunk@1361 -
This commit is contained in:
Jonas Maebe
parent
339f76182b
commit
cd3f064a33
@ -219,7 +219,9 @@ Unit aopt;
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End;
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{ more peephole optimizations }
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{ PeepHoleOptPass2;}
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{ free memory }
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{ if pass = last_pass then }
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PostPeepHoleOpts;
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{ free memory }
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clear;
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{ continue where we left off, BlockEnd is either the start of an }
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{ assembler block or nil}
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@ -298,6 +298,7 @@ Unit AoptObj;
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{ processor dependent methods }
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// if it returns true, perform a "continue"
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function PeepHoleOptPass1Cpu(var p: tai): boolean; virtual;
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function PostPeepHoleOptsCpu(var p: tai): boolean; virtual;
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End;
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Function ArrayRefsEq(const r1, r2: TReference): Boolean;
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@ -1094,7 +1095,19 @@ Unit AoptObj;
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procedure TAOptObj.PostPeepHoleOpts;
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var
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p: tai;
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begin
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p := BlockStart;
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//!!!! UsedRegs := [];
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while (p <> BlockEnd) Do
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begin
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//!!!! UpDateUsedRegs(UsedRegs, tai(p.next));
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if PostPeepHoleOptsCpu(p) then
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continue;
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//!!!!!!!! updateUsedRegs(UsedRegs,p);
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p:=tai(p.next);
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end;
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end;
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@ -1103,4 +1116,10 @@ Unit AoptObj;
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result := false;
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end;
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function TAOptObj.PostPeepHoleOptsCpu(var p: tai): boolean;
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begin
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result := false;
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end;
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End.
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@ -34,12 +34,15 @@ Type
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TCpuAsmOptimizer = class(TAsmOptimizer)
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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function PostPeepHoleOptsCpu(var p: tai): boolean; override;
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End;
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Implementation
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uses
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cutils, aasmcpu;
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cutils, aasmcpu, cgbase;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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@ -146,7 +149,138 @@ Implementation
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end;
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end;
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const
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modifyflags: array[tasmop] of tasmop =
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(a_none, a_add_, a_add_, a_addo_, a_addo_, a_addc_, a_addc_, a_addco_, a_addco_,
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a_adde_, a_adde_, a_addeo_, a_addeo_, {a_addi could be addic_ if sure doesn't disturb carry} a_none, a_addic_, a_addic_, a_none,
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a_addme_, a_addme_, a_addmeo_, a_addmeo_, a_addze_, a_addze_, a_addzeo_,
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a_addzeo_, a_and_, a_and_, a_andc_, a_andc_, a_andi_, a_andis_, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_cntlzw_, a_cntlzw_, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_divw_, a_divw_, a_divwo_, a_divwo_,
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a_divwu_, a_divwu_, a_divwuo_, a_divwuo_, a_none, a_none, a_none, a_eqv_,
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a_eqv_, a_extsb_, a_extsb_, a_extsh_, a_extsh_, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_mffs, a_mffs_, a_mfmsr, a_mfspr, a_mfsr,
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a_mfsrin, a_mftb, a_mtcrf, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_mulhw_,
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a_mulhw_, a_mulhwu_, a_mulhwu_, a_none, a_mullw_, a_mullw_, a_mullwo_,
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a_mullwo_, a_nand_, a_nand_, a_neg_, a_neg_, a_nego_, a_nego_, a_nor_, a_nor_,
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a_or_, a_or_, a_orc_, a_orc_, a_none, a_none, a_none, a_rlwimi_, a_rlwimi_,
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a_rlwinm_, a_rlwinm_, a_rlwnm_, a_rlwnm_, a_none, a_slw_, a_slw_, a_sraw_, a_sraw_,
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a_srawi_, a_srawi_,a_srw_, a_srw_, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_subf_, a_subf_, a_subfo_,
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a_subfo_, a_subfc_, a_subfc_, a_subfco_, a_subfco_, a_subfe_, a_subfe_,
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a_subfeo_, a_subfeo_, a_none, a_subfme_, a_subfme_, a_subfmeo_, a_subfmeo_,
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a_subfze_, a_subfze_, a_subfzeo_, a_subfzeo_, a_none, a_none, a_none,
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a_none, a_none, a_none, a_xor_, a_xor_, a_none, a_none,
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{ simplified mnemonics }
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a_none, a_none, a_subic_, a_subic_, a_sub_, a_sub_, a_subo_, a_subo_,
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a_subc_, a_subc_, a_subco_, a_subco_, a_none, a_none, a_none, a_none,
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a_extlwi_, a_extlwi_, a_extrwi_, a_extrwi_, a_inslwi_, a_inslwi_, a_insrwi_,
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a_insrwi_, a_rotlwi_, a_rotlwi_, a_rotlw_, a_rotlw_, a_slwi_, a_slwi_,
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a_srwi_, a_srwi_, a_clrlwi_, a_clrlwi_, a_clrrwi_, a_clrrwi_, a_clrslwi_,
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a_clrslwi_, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none {move to special prupose reg}, a_none {move from special purpose reg},
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a_none, a_none, a_none, a_none, a_mr_, a_mr_, a_not_, a_not_, a_none, a_none, a_none,
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a_none, a_none);
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function changetomodifyflags(p: taicpu): boolean;
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begin
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result := false;
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if (modifyflags[p.opcode] <> a_none) then
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begin
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p.opcode := modifyflags[p.opcode];
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result := true;
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end;
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end;
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function TCpuAsmOptimizer.PostPeepHoleOptsCpu(var p: tai): boolean;
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var
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next1: tai;
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begin
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result := false;
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case p.typ of
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_RLWINM_:
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begin
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// rlwinm_ is cracked on the G5, andi_/andis_ aren't
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if (taicpu(p).oper[2]^.val = 0) then
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if (taicpu(p).oper[3]^.val < 16) and
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(taicpu(p).oper[4]^.val < 16) then
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begin
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taicpu(p).opcode := A_ANDIS_;
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taicpu(p).oper[2]^.val :=
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((1 shl (16-taicpu(p).oper[3]^.val)) - 1) and
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not((1 shl (15-taicpu(p).oper[4]^.val)) - 1);
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taicpu(p).clearop(3);
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taicpu(p).clearop(4);
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taicpu(p).ops := 3;
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taicpu(p).opercnt := 2;
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end
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else if (taicpu(p).oper[3]^.val >= 16) and
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(taicpu(p).oper[4]^.val >= 16) then
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begin
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taicpu(p).opcode := A_ANDI_;
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taicpu(p).oper[2]^.val :=
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((1 shl (32-taicpu(p).oper[3]^.val)) - 1) and
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not((1 shl (31-taicpu(p).oper[4]^.val)) - 1);
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taicpu(p).clearop(3);
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taicpu(p).clearop(4);
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taicpu(p).ops := 3;
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taicpu(p).opercnt := 2;
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end;
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end;
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end;
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// change "integer operation with destination reg" followed by a
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// comparison to zero of that reg, with a variant of that integer
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// operation which sets the flags (if it exists)
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if not(result) and
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(taicpu(p).ops >= 2) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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((taicpu(next1).opcode = A_CMPWI) or
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(taicpu(next1).opcode = A_CMPLWI)) and
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// make sure it the result goes to cr0
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(((taicpu(next1).ops = 2) and
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(taicpu(next1).oper[1]^.val = 0) and
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(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg)) or
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((taicpu(next1).ops = 3) and
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(taicpu(next1).oper[2]^.val = 0) and
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(taicpu(next1).oper[0]^.typ = top_reg) and
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(getsupreg(taicpu(next1).oper[0]^.reg) = RS_CR0) and
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(taicpu(next1).oper[1]^.reg = taicpu(p).oper[0]^.reg))) and
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changetomodifyflags(taicpu(p)) then
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begin
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asml.remove(next1);
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next1.free;
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result := true;
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end;
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end;
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end;
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end;
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begin
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casmoptimizer:=TCpuAsmOptimizer;
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End.
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