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* fixes not(<qwordbool>) on arm
* fixes not(<(q/l)wordbool>) on avr git-svn-id: trunk@38263 -
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compiler
@ -310,6 +310,8 @@ implementation
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*****************************************************************************}
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procedure tarmnotnode.second_boolean;
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var
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tmpreg : TRegister;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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@ -328,7 +330,14 @@ implementation
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0));
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if is_64bit(resultdef) then
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begin
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tmpreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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{ OR low and high parts together }
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ORR,left.location.register64.reglo,left.location.register64.reghi,tmpreg),PF_S));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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@ -57,7 +57,7 @@ implementation
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procedure tavrnotnode.second_boolean;
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var
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tmpreg : tregister;
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tmpreg,lreg : tregister;
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i : longint;
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begin
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if not handle_locjump then
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@ -74,12 +74,15 @@ implementation
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,0));
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tmpreg:=left.location.register;
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{ avr has no cpci, so we use the first register as "zero" register }
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tmpreg:=left.location.register;
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for i:=2 to tcgsize2size[left.location.size] do
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg,left.location.register));
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if i=5 then
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tmpreg:=left.location.registerhi
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else
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tmpreg:=cg.GetNextReg(tmpreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,NR_R1,tmpreg));
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end;
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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