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* fixes not(<qwordbool>) on arm

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* fixes not(<(q/l)wordbool>) on avr

git-svn-id: trunk@38263 -
This commit is contained in:
florian 2018-02-16 22:38:35 +00:00
parent 15bdce0a6a
commit cd41312a8f
2 changed files with 17 additions and 5 deletions
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11
compiler/arm/narmmat.pas
View File

@ -310,6 +310,8 @@ implementation
*****************************************************************************} *****************************************************************************}
procedure tarmnotnode.second_boolean; procedure tarmnotnode.second_boolean;
var
tmpreg : TRegister;
begin begin
{ if the location is LOC_JUMP, we do the secondpass after the { if the location is LOC_JUMP, we do the secondpass after the
labels are allocated labels are allocated
@ -328,7 +330,14 @@ implementation
begin begin
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true); hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0)); if is_64bit(resultdef) then
begin
tmpreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
{ OR low and high parts together }
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ORR,left.location.register64.reglo,left.location.register64.reghi,tmpreg),PF_S));
end
else
current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0));
location_reset(location,LOC_FLAGS,OS_NO); location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=F_EQ; location.resflags:=F_EQ;
end; end;

11
compiler/avr/navrmat.pas
View File

@ -57,7 +57,7 @@ implementation
procedure tavrnotnode.second_boolean; procedure tavrnotnode.second_boolean;
var var
tmpreg : tregister; tmpreg,lreg : tregister;
i : longint; i : longint;
begin begin
if not handle_locjump then if not handle_locjump then
@ -74,12 +74,15 @@ implementation
begin begin
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true); hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,0)); current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,0));
tmpreg:=left.location.register;
{ avr has no cpci, so we use the first register as "zero" register } tmpreg:=left.location.register;
for i:=2 to tcgsize2size[left.location.size] do for i:=2 to tcgsize2size[left.location.size] do
begin begin
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg,left.location.register)); if i=5 then
tmpreg:=left.location.registerhi
else
tmpreg:=cg.GetNextReg(tmpreg);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,NR_R1,tmpreg));
end; end;
location_reset(location,LOC_FLAGS,OS_NO); location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=F_EQ; location.resflags:=F_EQ;