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* moved support for passing floating point values in integer registers from
platform-dependent ifdef'ed code in ncgcal to generic code cgobj git-svn-id: trunk@15316 -
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@ -2632,17 +2632,35 @@ implementation
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procedure tcg.a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const cgpara : TCGPara);
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procedure tcg.a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const cgpara : TCGPara);
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var
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var
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href : treference;
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href : treference;
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hsize: tcgsize;
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begin
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begin
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cgpara.check_simple_location;
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case cgpara.location^.loc of
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case cgpara.location^.loc of
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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begin
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cgpara.check_simple_location;
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a_loadfpu_ref_reg(list,size,size,ref,cgpara.location^.register);
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a_loadfpu_ref_reg(list,size,size,ref,cgpara.location^.register);
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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begin
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cgpara.check_simple_location;
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reference_reset_base(href,cgpara.location^.reference.index,cgpara.location^.reference.offset,cgpara.alignment);
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reference_reset_base(href,cgpara.location^.reference.index,cgpara.location^.reference.offset,cgpara.alignment);
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{ concatcopy should choose the best way to copy the data }
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{ concatcopy should choose the best way to copy the data }
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g_concatcopy(list,ref,href,tcgsize2size[size]);
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g_concatcopy(list,ref,href,tcgsize2size[size]);
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end;
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end;
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LOC_REGISTER,LOC_CREGISTER:
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begin
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{ force integer size }
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hsize:=int_cgsize(tcgsize2size[size]);
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{$ifndef cpu64bitalu}
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if (hsize in [OS_S64,OS_64]) then
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cg64.a_load64_ref_cgpara(list,ref,cgpara)
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else
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{$endif not cpu64bitalu}
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begin
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cgpara.check_simple_location;
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a_load_ref_cgpara(list,hsize,ref,cgpara)
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end;
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end
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else
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else
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internalerror(200402201);
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internalerror(200402201);
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end;
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end;
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@ -216,36 +216,9 @@ implementation
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,false);
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,false);
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cg.a_loadmm_reg_cgpara(current_asmdata.CurrAsmList,left.location.size,left.location.register,tempcgpara,mms_movescalar);
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cg.a_loadmm_reg_cgpara(current_asmdata.CurrAsmList,left.location.size,left.location.register,tempcgpara,mms_movescalar);
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end;
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end;
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{$ifdef cpu64bitalu}
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{ Some targets pass floats in normal registers }
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LOC_REGISTER,
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LOC_CREGISTER :
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begin
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location_force_mem(current_asmdata.CurrAsmList,left.location);
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{ force integer size }
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left.location.size:=int_cgsize(tcgsize2size[left.location.size]);
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cg.a_load_ref_cgpara(current_asmdata.CurrAsmList,left.location.size,left.location.reference,tempcgpara);
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end;
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{$endif cpu64bitalu}
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{$ifdef powerpc}
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LOC_REGISTER,
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LOC_CREGISTER :
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begin
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{ aix abi passes floats of varargs in both fpu and }
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{ integer registers }
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location_force_mem(current_asmdata.CurrAsmList,left.location);
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{ force integer size }
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left.location.size:=int_cgsize(tcgsize2size[left.location.size]);
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if (left.location.size in [OS_32,OS_S32]) then
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cg.a_load_ref_cgpara(current_asmdata.CurrAsmList,left.location.size,left.location.reference,tempcgpara)
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else
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cg64.a_load64_ref_cgpara(current_asmdata.CurrAsmList,left.location.reference,tempcgpara);
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end;
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{$endif powerpc}
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{$if defined(sparc) or defined(arm) or defined(m68k)}
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{ sparc and arm pass floats in normal registers }
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LOC_REGISTER,
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LOC_REGISTER,
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LOC_CREGISTER,
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LOC_CREGISTER,
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{$endif sparc}
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LOC_REFERENCE,
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LOC_REFERENCE,
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LOC_CREFERENCE,
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LOC_CREFERENCE,
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LOC_FPUREGISTER,
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LOC_FPUREGISTER,
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