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m68k: basic 68881 fpu support. probably still broken at umpzillion places, and mostly untested, but at least it builds the RTL and all packages successfully with -Cp68020 -Cf68881 instead of dying with random internalerrors() and now even emits actual FPU opcodes.
git-svn-id: trunk@29370 -
This commit is contained in:
Károly Balogh
parent
588256f79a
commit
d000b1bc7c
@ -464,6 +464,7 @@ type
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result:=operand_read;
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case opcode of
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// CPU opcodes
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A_MOVE, A_MOVEQ, A_MOVEA, A_MVZ, A_MVS, A_MOV3Q, A_LEA:
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if opnr=1 then
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result:=operand_write;
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@ -483,6 +484,17 @@ type
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result:=operand_readwrite;
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A_TST,A_CMP,A_CMPI:
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begin end; { Do nothing, default operand_read is fine here. }
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// FPU opcodes
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A_FMOVE:
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if opnr=1 then
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result:=operand_write;
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A_FADD, A_FSUB, A_FMUL, A_FDIV:
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if opnr=1 then
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result:=operand_readwrite;
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A_FCMP:
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begin end; { operand_read }
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else begin
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internalerror(2004040903);
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end;
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@ -508,17 +520,17 @@ type
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function spilling_create_store(r:tregister; const ref:treference):Taicpu;
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begin
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case getregtype(r) of
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R_INTREGISTER :
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result:=taicpu.op_reg_ref(A_MOVE,S_L,r,ref);
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R_ADDRESSREGISTER :
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result:=taicpu.op_reg_ref(A_MOVE,S_L,r,ref);
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R_FPUREGISTER :
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case getregtype(r) of
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R_INTREGISTER :
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result:=taicpu.op_reg_ref(A_MOVE,S_L,r,ref);
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R_ADDRESSREGISTER :
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result:=taicpu.op_reg_ref(A_MOVE,S_L,r,ref);
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R_FPUREGISTER :
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// no need to handle sizes here
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result:=taicpu.op_reg_ref(A_FMOVE,S_FS,r,ref);
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else
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internalerror(200602012);
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end;
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end;
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end;
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@ -964,20 +964,16 @@ unit cgcpu;
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var
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instr : taicpu;
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begin
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{ in emulation mode, only 32-bit single is supported }
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if (cs_fp_emulation in current_settings.moduleswitches) or (current_settings.fputype=fpu_soft) then
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg1,reg2)
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else
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instr:=taicpu.op_reg_reg(A_FMOVE,tcgsize2opsize[tosize],reg1,reg2);
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add_move_instruction(instr);
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list.concat(instr);
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instr:=taicpu.op_reg_reg(A_FMOVE,S_FX,reg1,reg2);
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add_move_instruction(instr);
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list.concat(instr);
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end;
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procedure tcg68k.a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister);
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var
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opsize : topsize;
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href : treference;
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var
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opsize : topsize;
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href : treference;
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begin
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opsize := tcgsize2opsize[fromsize];
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{ extended is not supported, since it is not available on Coldfire }
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@ -985,30 +981,21 @@ unit cgcpu;
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internalerror(20020729);
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href := ref;
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fixref(list,href);
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{ in emulation mode, only 32-bit single is supported }
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if (cs_fp_emulation in current_settings.moduleswitches) or (current_settings.fputype=fpu_soft) then
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list.concat(taicpu.op_ref_reg(A_MOVE,S_L,href,reg))
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else
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begin
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list.concat(taicpu.op_ref_reg(A_FMOVE,opsize,href,reg));
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if (tosize < fromsize) then
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a_loadfpu_reg_reg(list,fromsize,tosize,reg,reg);
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end;
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list.concat(taicpu.op_ref_reg(A_FMOVE,opsize,href,reg));
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end;
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procedure tcg68k.a_loadfpu_reg_ref(list: TAsmList; fromsize,tosize: tcgsize; reg: tregister; const ref: treference);
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var
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opsize : topsize;
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opsize : topsize;
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href : treference;
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begin
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opsize := tcgsize2opsize[tosize];
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{ extended is not supported, since it is not available on Coldfire }
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if opsize = S_FX then
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internalerror(20020729);
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{ in emulation mode, only 32-bit single is supported }
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if (cs_fp_emulation in current_settings.moduleswitches) or (current_settings.fputype=fpu_soft) then
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list.concat(taicpu.op_reg_ref(A_MOVE,S_L,reg, ref))
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else
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list.concat(taicpu.op_reg_ref(A_FMOVE,opsize,reg, ref));
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href := ref;
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fixref(list,href);
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list.concat(taicpu.op_reg_ref(A_FMOVE,opsize,reg,href));
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end;
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@ -1018,8 +1005,7 @@ unit cgcpu;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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case size of
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OS_F64:
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cg64.a_load64_ref_cgpara(list,ref,cgpara);
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OS_F64,
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OS_F32:
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a_load_ref_cgpara(list,size,ref,cgpara);
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else
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@ -138,56 +138,53 @@ implementation
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if nf_swapped in flags then
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swapleftright;
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// put both operands in a register
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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case current_settings.fputype of
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fpu_68881:
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begin
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// put both operands in a register
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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// initialize de result
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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if left.location.loc = LOC_FPUREGISTER then
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location.register := left.location.register
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else if right.location.loc = LOC_FPUREGISTER then
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location.register := right.location.register
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else
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location.register := cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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// initialize the result
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register := cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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// emit the actual operation
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{
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,
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right.location.register))
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}
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// emit the actual operation
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FMOVE,S_FX,left.location.register,location.register));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,S_FX,right.location.register,location.register));
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end;
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else
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// softfpu should be handled in pass1, others are not yet supported...
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internalerror(2015010201);
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end;
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end;
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procedure t68kaddnode.second_cmpfloat;
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begin
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pass_left_right;
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{
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if (nf_swapped in flags) then
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swapleftright;
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}
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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{
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if nodetype in [equaln,unequaln] then
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMF,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]))
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else
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMFE,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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case current_settings.fputype of
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fpu_68881:
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(false);
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}
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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// emit compare
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FCMP,S_FX,right.location.register,left.location.register));
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location.resflags:=getresflags(false);
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end;
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else
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// softfpu should be handled in pass1, others are not yet supported...
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internalerror(2015010201);
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end;
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end;
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@ -68,8 +68,14 @@ implementation
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end
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else
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{ converting a 64bit integer to a float requires a helper }
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if is_64bitint(left.resultdef) then
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if is_64bitint(left.resultdef) or
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is_currency(left.resultdef) then
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begin
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{ hack to avoid double division by 10000, as it's
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already done by typecheckpass.resultdef_int_to_real }
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if is_currency(left.resultdef) then
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left.resultdef := s64inttype;
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if is_signed(left.resultdef) then
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fname := 'fpc_int64_to_double'
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else
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